Alternatives and similar repositories for Embedded-Design-Tutorials

Users that are interested in Embedded-Design-Tutorials are comparing it to the libraries listed below

• Xilinx / Vivado-Design-Tutorials
  ☆202Updated 2 weeks ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆84Updated last year
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆65Updated 2 months ago
• Xilinx / XilinxBoardStore
  ☆286Updated this week
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆98Updated last week
• ATaylorCEngFIET / Hackster
  Files used with hackster examples
  ☆146Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆122Updated 6 years ago
• Xilinx-Wiki-Projects / software-prototypes
  ☆69Updated 10 months ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆128Updated 10 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆133Updated 3 weeks ago
• jamieiles / uart
  Verilog UART
  ☆163Updated 11 years ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆102Updated 5 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆61Updated 3 years ago
• fpgadeveloper / fpga-drive-aximm-pcie
  Example designs for FPGA Drive FMC
  ☆246Updated 4 months ago
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆215Updated last week
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆220Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆88Updated 3 years ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆85Updated 2 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆134Updated 2 years ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆126Updated 5 years ago
• cathalmccabe / PYNQ_tutorials
  ☆90Updated last year
• westonb / OV7670-Verilog
  Verilog modules required to get the OV7670 camera working
  ☆70Updated 6 years ago
• fpgadeveloper / zedboard-axi-dma
  Demonstration of the AXI DMA engine on the ZedBoard
  ☆53Updated 4 years ago
• Avnet / hdl
  ☆111Updated last month
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆81Updated 5 years ago
• jijingg / Spinal-bootcamp
  SpinalHDL-tutorial based on Jupyter Notebook
  ☆135Updated 11 months ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆126Updated 5 months ago
• Digilent / Zybo-Z7-20-pcam-5c
  ☆55Updated 2 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆333Updated last year
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆102Updated 9 months ago