world-of-open-source / WoS-Events
This repository contains information required to successfully complete Hands-on Sessions of various events conducted under WoS.
☆9Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for WoS-Events
- the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.☆39Updated 4 years ago
- Digital Design verilog tricky problems having industry standards☆22Updated 4 years ago
- Processor repo☆47Updated 10 years ago
- Design of a 16-Bit CPU using Verilog☆24Updated 5 years ago
- ☆597Updated 3 weeks ago
- Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.☆304Updated 2 years ago
- Solution to COA LAB Assgn, IIT Kharagpur☆35Updated 5 years ago
- A collection of commonly asked RTL design interview questions☆21Updated 7 years ago
- RapidStream TAPA compiles task-parallel HLS program into high-frequency FPGA accelerators.☆155Updated this week
- This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum☆51Updated 2 years ago
- ☆141Updated last week
- cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python☆1,804Updated this week
- The RISC-V Application Profiler is a Python-based tool designed to help software developers optimize the performance of their application…☆30Updated 11 months ago
- Design and Analysis of CMOS Inverter using the sky130 pdk and various open source tools☆98Updated 2 years ago
- Open Logic HDL Standard Library☆345Updated last week
- Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern he…☆219Updated this week
- ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture …☆520Updated this week
- VHDL 2008/93/87 simulator☆2,386Updated this week
- Xilinx Tcl Store☆349Updated 2 weeks ago
- This project shows how to model a 10-bit pipeline ADC and a 10-bit DAC using ideal components. Used vdc, vpulse, vcvs, switch, res, cap, …☆21Updated 5 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆232Updated 3 weeks ago
- 100 Days Of RTL is a personal challenge designed to help improve skills and knowledge in digital circuit design. The challenge involves c…☆25Updated last year
- BaseJump STL: A Standard Template Library for SystemVerilog☆522Updated this week
- BookSim 2.0☆275Updated 4 months ago
- An abstraction library for interfacing EDA tools☆637Updated last week
- Software and Hardware models of Approximate Carry-Lookahead Adder with Intelligent Carry Judgement and Correction☆12Updated 2 years ago
- opensource EDA tool flor VLSI design☆29Updated last year
- ☆255Updated 2 weeks ago
- A git-friendly Vivado wrapper☆217Updated 5 months ago