Verdvana / OV5640_SDRAMLinks
OV5640摄像头驱动及TFT屏幕显示
☆15Updated 6 years ago
Alternatives and similar repositories for OV5640_SDRAM
Users that are interested in OV5640_SDRAM are comparing it to the libraries listed below
Sorting:
- Source code for Zynq OLED controller☆15Updated 4 years ago
- 一种基于FPGA平台的实时视频去雾系统项目代码,其中bit流文件可以直接下载到PYNQ-Z2开发板上,通过usb和hdmi设备输入有雾视频,将去雾后的视频输出到显示屏上。c++源代码部分是我们的去雾IP核的源代码。☆20Updated 5 years ago
- 基于verilog实现了ISP图像处理IP☆287Updated 2 years ago
- Undergraduate digital circuit laboratory☆27Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆206Updated 2 years ago
- 基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现☆349Updated 2 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆94Updated 8 years ago
- AXI4-Stream FIR filter IP☆19Updated 2 years ago
- FPGA project☆229Updated 3 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆39Updated 2 years ago
- Constrast limited adaptive histogram equlization based on Verilog☆37Updated 2 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆44Updated last year
- image processing based FPGA☆114Updated 4 years ago
- Vivado诸多IP,包括图像处理等☆229Updated last year
- FPGA☆158Updated last year
- A novel architectural design for stitching video streams in real-time on an FPGA.☆128Updated 3 years ago
- 基于FPGA和ov5640的实时图像采集及灰度转换系统☆17Updated last year
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆281Updated last year
- The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…☆46Updated last year
- ☆141Updated 10 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆74Updated 4 years ago
- ☆283Updated last year
- WM8731 Audio CODEC using Verilog (DE2-115)☆10Updated 6 years ago
- 2023集创赛紫光同创杯一等奖项目☆127Updated last year
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆252Updated 2 years ago
- A hardware implementation of CNN, written by Verilog and synthesized on FPGA☆239Updated 6 years ago
- it is a set for all the respository of the project.☆98Updated 6 years ago
- FPGA图像处理仿真平台☆27Updated 3 years ago
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆187Updated last year
- 包含了SOC设计中的通用IP,如外设、总线结构、基础、验证等☆118Updated last week