ucb-bar / autophase
☆31Updated 3 years ago
Alternatives and similar repositories for autophase:
Users that are interested in autophase are comparing it to the libraries listed below
- EQueue Dialect☆40Updated 3 years ago
- agile hardware-software co-design☆46Updated 3 years ago
- ICCAD'23 Best Paper Award candidate: Robust GNN-based Representation Learning for HLS☆18Updated 11 months ago
- NeuroVectorizer is a framework that uses deep reinforcement learning (RL) to predict optimal vectorization compiler pragmas for for loops…☆94Updated 2 years ago
- ☆10Updated 6 months ago
- ☆16Updated last year
- DAC'22 paper: "Automated Accelerator Optimization Aided by Graph Neural Networks"☆40Updated last year
- GPU-enabled Hardware Fuzzer using Genetic Algorithm☆17Updated last year
- We solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop …☆18Updated 3 years ago
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆58Updated 6 months ago
- Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits☆26Updated 8 months ago
- A portable framework to map DFG (dataflow graph, representing an application) on spatial accelerators.☆36Updated 2 years ago
- Multi-target compiler for Sum-Product Networks, based on MLIR and LLVM.☆23Updated 5 months ago
- HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)☆17Updated 7 months ago
- ☆91Updated last year
- CGRA Compilation Framework☆83Updated last year
- ☆18Updated this week
- A PIM instrumentation, compilation, execution, simulation, and evaluation repository for BLIMP-style architectures.☆18Updated 2 years ago
- ILA Model Database☆22Updated 4 years ago
- ☆11Updated 3 months ago
- HeteroCL-MLIR dialect for accelerator design☆40Updated 7 months ago
- ☆17Updated 3 years ago
- A graph linear algebra overlay☆51Updated 2 years ago
- DATuner Repository☆18Updated 6 years ago
- DATE'24 paper: "Hierarchical Source-to-Post-Route QoR Prediction in High-Level Synthesis with GNNs"☆17Updated 4 months ago
- E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis (DAC 2024)☆29Updated 9 months ago
- ☆24Updated 4 years ago
- A high-level performance analysis tool for FPGA-based accelerators☆20Updated 7 years ago
- Polyhedral High-Level Synthesis in MLIR☆30Updated 2 years ago
- ☆16Updated 2 weeks ago