ttsiodras / grlib-gpl
My optimistic - yet unexpectedly successful - attempt to create a LEON3 inside my FPGA boards (ZestSC1, Pano Logic G2)
☆12Updated 4 years ago
Alternatives and similar repositories for grlib-gpl
Users that are interested in grlib-gpl are comparing it to the libraries listed below
Sorting:
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆11Updated 4 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board☆37Updated 2 years ago
- A re-creation of a Cosmac ELF computer, Coded in SpinalHDL☆40Updated 4 years ago
- mystorm sram test☆27Updated 7 years ago
- Fully featured implementation of Inter-IC (I2C) bus master for FPGAs☆27Updated 4 years ago
- RV32I single cycle simulation on open-source software Logisim.☆19Updated 2 years ago
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 3 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆16Updated 6 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- VGA-compatible text mode functionality☆17Updated 4 years ago
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- Design to connect Lattice Ultraplus FPGA to LH154Q01 Display☆28Updated 6 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- Learn how to create your own 32-bit system from scratch.☆13Updated 3 years ago
- Minimal microprocessor☆20Updated 7 years ago
- Retro computing on the Ulx3s ECP5 FPGA board☆24Updated 3 years ago
- FPGA 8-Bit TV80 SoC for Lattice iCE40 with complete open-source toolchain flow using yosys and SDCC☆57Updated 2 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- Picorv32 SoC that uses only BRAM, not flash memory☆12Updated 6 years ago
- A very simple RISC-V ISA emulator.☆37Updated 4 years ago
- Tools for FPGA development.☆45Updated 2 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12Updated 5 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago