Alternatives and similar repositories for grlib-gpl

Users that are interested in grlib-gpl are comparing it to the libraries listed below

• lawrie / ulx3s_examples
  Example Verilog code for Ulx3s
  ☆40Updated 3 years ago
• rschlaikjer / fpga-3-softcores
  Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware
  ☆12Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆41Updated 4 months ago
• hdl-util / vga-text-mode
  VGA-compatible text mode functionality
  ☆17Updated 5 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 months ago
• openXC7 / openXC7-snap
  snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support
  ☆28Updated 11 months ago
• hdl-util / i2c
  Fully featured implementation of Inter-IC (I2C) bus master for FPGAs
  ☆27Updated 5 years ago
• mattvenn / fpga-sram
  mystorm sram test
  ☆27Updated 7 years ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 4 months ago
• blackmesalabs / s7_mini_fpga
  Example designs for the Spartan7 "S7 Mini" FPGA board
  ☆28Updated 6 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• nand2mario / ddr3-tang-primer-20k
  DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.
  ☆55Updated last year
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• Wren6991 / Hazard5
  5-stage RISC-V CPU, originally developed for RISCBoy
  ☆27Updated last year
• ironsteel / nes_ecp5
  NES FPGA implementation synthesized for the ulx3s ecp5 based fpga board
  ☆37Updated 2 years ago
• twj42 / PanoLogicG2_ReverseEngineering
  A repository for a random collection of stuff pertaining to reverse engineering the Pano Logic G2 "zero" client
  ☆34Updated 6 years ago
• lawrie / ulx3s_bit_streams
  Bit streams forthe Ulx3s ECP5 device
  ☆17Updated 2 years ago
• tomverbeure / intel_jtag_primitive_blog
  How to use the Intel JTAG primitive without using virtual JTAG
  ☆17Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆90Updated 5 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆60Updated 6 years ago
• lawrie / ulx3s_retro
  Retro computing on the Ulx3s ECP5 FPGA board
  ☆24Updated 3 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆27Updated 3 years ago
• rob-ng15 / Silice-Playground
  Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice
  ☆35Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated 3 weeks ago
• projf / fpgatools
  Tools for FPGA development.
  ☆45Updated 2 years ago
• lmEshoo / sp-i586
  soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…
  ☆32Updated 8 years ago
• defparam / PCI2Nano-PCB
  An FPGA/PCI Device Reference Platform
  ☆28Updated 4 years ago
• grayresearch / s3ga
  S3GA: a simple scalable serial FPGA
  ☆10Updated 2 years ago
• OpenCAPI / omi_device_ice
  An example OMI Device FPGA with 2 DDR4 memory ports
  ☆16Updated 2 years ago
• b-dmitry1 / BIOS
  Very compact (8KB) embedded x86 BIOS for FPGA/emulators/386EX
  ☆17Updated 3 years ago