ttsiodras / grlib-gplLinks
My optimistic - yet unexpectedly successful - attempt to create a LEON3 inside my FPGA boards (ZestSC1, Pano Logic G2)
☆12Updated 4 years ago
Alternatives and similar repositories for grlib-gpl
Users that are interested in grlib-gpl are comparing it to the libraries listed below
Sorting:
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- Example Risc-V SoC with VexRiscv, custom peripherals and bare metal firmware☆13Updated 4 years ago
- Tools for FPGA development.☆47Updated this week
- SDRAM controller optimized to a memory bandwidth of 316MB/s☆27Updated 3 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- ULX3S FPGA, RISC-V, ESP32 toolchain installer scripts☆39Updated 4 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set☆61Updated last month
- YARI is a high performance open source FPGA soft-core RISC implementation, binary compatible with MIPS I. The distribution package includ…☆45Updated 7 months ago
- Retro computing on the Ulx3s ECP5 FPGA board☆24Updated 3 years ago
- Minimal microprocessor☆21Updated 8 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆60Updated 6 years ago
- Reusable Verilog 2005 components for FPGA designs☆45Updated 4 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆53Updated 4 years ago
- Update IceStudio to support ColorLight 5A-75X, i5 and ICeSugar Pro FPGA boards☆48Updated last year
- soft processor core compatible with i586 instruction set(Intel Pentium) developped on Nexys4 board boots linux kernel with a ramdisk cont…☆32Updated 8 years ago
- 16 bit RISC-V proof of concept☆24Updated 10 months ago
- Multi-function, universal, fixed-point CORDIC☆15Updated 3 years ago
- VGA-compatible text mode functionality☆17Updated 5 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- A bit-serial CPU☆19Updated 5 years ago
- 5-stage RISC-V CPU, originally developed for RISCBoy☆28Updated 2 years ago
- Beginner-friendly Verilog based examples for the ULX3S FPGA board.☆11Updated 3 years ago
- DDR3 controller for Tang Primer 20K (Gowin GW2A-18C fpga). DDR3-800 speed and low latency.☆55Updated last year
- Minimal ZX Spectrum for Ulx3s ECP5 board☆12Updated 5 years ago
- Bit streams forthe Ulx3s ECP5 device☆17Updated 2 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Updated 6 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- IceCore Ice40 HX based modular core☆46Updated 4 years ago