stnolting / wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
☆21Updated 3 years ago
Alternatives and similar repositories for wb_spi_bridge
Users that are interested in wb_spi_bridge are comparing it to the libraries listed below
Sorting:
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- CologneChip GateMate FPGA Module: GMM-7550☆21Updated last year
- Project Peppercorn - GateMate FPGA Bitstream Documentation☆18Updated 2 weeks ago
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- Virtual development board for HDL design☆42Updated 2 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆40Updated last week
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Specification of the Wishbone SoC Interconnect Architecture☆45Updated 2 years ago
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- LiteX development baseboards arround the SQRL Acorn.☆63Updated last month
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- PMOD boards for ULX3S☆43Updated last year
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- sump3 logic analyzer☆19Updated 2 weeks ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆30Updated last year
- A configurable USB 2.0 device core☆31Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆42Updated 2 months ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆44Updated this week
- Small footprint and configurable Inter-Chip communication cores☆57Updated 3 weeks ago
- Example Verilog code for Ulx3s☆40Updated 3 years ago
- System on Chip toolkit for nMigen☆19Updated 5 years ago
- Examples and design pattern for VHDL verification☆15Updated 9 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated 3 months ago
- RISC-V Processor written in Amaranth HDL☆37Updated 3 years ago
- Development board for GateMateA1 CCGM1A1 FPGA from Cologne Chip with PS2 VGA 64Mbit RAM RP2040☆29Updated 5 months ago
- USB virtual model in C++ for Verilog☆30Updated 6 months ago
- A padring generator for ASICs☆25Updated last year
- Experiments with Yosys cxxrtl backend☆48Updated 3 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- Board and connector definition files for nMigen☆30Updated 4 years ago