stnolting / wb_spi_bridgeLinks
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
☆22Updated 3 years ago
Alternatives and similar repositories for wb_spi_bridge
Users that are interested in wb_spi_bridge are comparing it to the libraries listed below
Sorting:
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆55Updated 3 weeks ago
- CologneChip GateMate FPGA Module: GMM-7550☆24Updated last week
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆30Updated 3 years ago
- LiteX development baseboards arround the SQRL Acorn.☆70Updated 7 months ago
- Virtual development board for HDL design☆42Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- A configurable USB 2.0 device core☆31Updated 5 years ago
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆29Updated last year
- A reconfigurable logic circuit made of identical rotatable tiles.☆23Updated 3 years ago
- Nitro USB FPGA core☆86Updated last year
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆45Updated this week
- USB virtual model in C++ for Verilog☆31Updated last year
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆32Updated 2 years ago
- ☆70Updated last year
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Updated 2 years ago
- PicoRV☆43Updated 5 years ago
- System on Chip toolkit for Amaranth HDL☆93Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆43Updated 4 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆107Updated last month
- Tool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.☆22Updated last year
- ☆42Updated 5 years ago
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 4 years ago
- User-friendly explanation of Yosys options☆112Updated 4 years ago
- Reusable Verilog 2005 components for FPGA designs☆47Updated 7 months ago
- Specification of the Wishbone SoC Interconnect Architecture☆46Updated 3 years ago
- assorted library of utility cores for amaranth HDL☆96Updated last year
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆91Updated 7 years ago
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆45Updated 4 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 3 years ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago