stnolting / wb_spi_bridge
🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).
☆21Updated 3 years ago
Alternatives and similar repositories for wb_spi_bridge:
Users that are interested in wb_spi_bridge are comparing it to the libraries listed below
- A reconfigurable logic circuit made of identical rotatable tiles.☆21Updated 3 years ago
- A configurable USB 2.0 device core☆30Updated 4 years ago
- Constraint files for Hardware Description Language (HDL) designs targeting FPGA boards☆43Updated this week
- A usable language reference for VHDL that is concise, direct, and easy to understand.☆25Updated last year
- 🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.☆29Updated 2 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- ☆22Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆36Updated 3 years ago
- Virtual development board for HDL design☆40Updated last year
- ☆22Updated last year
- Drop In USB CDC ACM core for iCE40 FPGA☆34Updated 3 years ago
- LunaPnR is a place and router for integrated circuits☆46Updated 3 months ago
- Experimental FPGA project for streaming two MIPI CSI camera streams to an HDMI monitor using a ULX3S FPGA board☆28Updated last year
- PicoRV☆44Updated 5 years ago
- The ILA allows you to perform in-system debugging of your designs on the GateMate FPGA at runtime. All signals of your design inside the …☆50Updated last month
- Library of reusable VHDL components☆27Updated 11 months ago
- an inverter drawn in magic with makefile to simulate☆26Updated 2 years ago
- Examples and design pattern for VHDL verification☆15Updated 8 years ago
- Device description files (architecture, timing, configuration bitstream, and general documentation) for EOS S3 MCU+eFPGA SoC☆25Updated 3 years ago
- PMOD boards for ULX3S☆42Updated last year
- Specification of the Wishbone SoC Interconnect Architecture☆43Updated 2 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated this week
- USB virtual model in C++ for Verilog☆29Updated 4 months ago
- A padring generator for ASICs☆25Updated last year
- snap package for nextpnr PnR FPGA toolchain for Xilinx 7 series FPGAs, with Spartan7, Artix7, Zynq7 and Kintex7 support☆28Updated 7 months ago
- ☆12Updated 3 years ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆38Updated last year
- sump3 logic analyzer☆18Updated 2 months ago
- Experiments with Yosys cxxrtl backend☆47Updated last month