shivarajagopal / ece5775-final
Voice Recognition using FPGA-Based Neural Networks
☆11Updated 8 years ago
Alternatives and similar repositories for ece5775-final:
Users that are interested in ece5775-final are comparing it to the libraries listed below
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆28Updated 7 years ago
- Expiremental Speech Recognition System using VHDL & MATLAB.☆44Updated 6 years ago
- A multi-board Extended Kalman Filter (EKF)☆31Updated 6 years ago
- Verilog library for implementing neural networks.☆26Updated 10 years ago
- Adding PR to the PYNQ Overlay☆17Updated 7 years ago
- Verilog Convolutional Neural Network on PYNQ☆28Updated 6 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆100Updated 4 years ago
- Source code of basic Xilinx Vivado HLS image processing tutorial using HLS openCV functions☆25Updated 6 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆42Updated 9 years ago
- An implementation of the CORDIC algorithm in Verilog.☆86Updated 6 years ago
- Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.☆28Updated 4 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- FGPU is a soft GPU architecture general purpose computing☆56Updated 4 years ago
- This repo is for ECE44x (Fall2015-Spring2016)☆19Updated 6 years ago
- Hot & Spicy tool suite☆23Updated 3 years ago
- openHMC - an open source Hybrid Memory Cube Controller☆46Updated 8 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆99Updated 6 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆32Updated 6 years ago
- A convolutional neural network implemented in hardware (verilog)☆155Updated 7 years ago
- Premade bitstreams and block designs to complemented the PYNQ overlay tutorial☆39Updated 3 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Updated 7 years ago
- Parallel Array of Simple Cores. Multicore processor.☆94Updated 5 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 8 years ago
- ☆104Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆60Updated 8 years ago
- IP operations in verilog (simulation and implementation on ice40)☆54Updated 5 years ago
- Image Processing on FPGA using VHDL☆40Updated 10 years ago