shivarajagopal / ece5775-final
Voice Recognition using FPGA-Based Neural Networks
☆11Updated 8 years ago
Alternatives and similar repositories for ece5775-final:
Users that are interested in ece5775-final are comparing it to the libraries listed below
- Expiremental Speech Recognition System using VHDL & MATLAB.☆46Updated 7 years ago
- Adding PR to the PYNQ Overlay☆17Updated 8 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆28Updated 8 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆107Updated 5 years ago
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Updated 7 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 6 years ago
- An implementation of the CORDIC algorithm in Verilog.☆93Updated 6 years ago
- Collection of hardware description languages writings and code snippets☆27Updated 10 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆44Updated 9 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Updated 8 years ago
- Parallel Array of Simple Cores. Multicore processor.☆97Updated 5 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- Hardware and Software Co-design implementations☆14Updated 5 years ago
- A multi-board Extended Kalman Filter (EKF)☆31Updated 6 years ago
- Verilog library for implementing neural networks.☆26Updated 10 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆58Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆79Updated 5 years ago
- synthesizable FFT IP block for FPGA designs☆32Updated 6 years ago
- ☆18Updated last year
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- This a complete and fully working Viola-Jones face detection algorithm described in VHDL and verified on the DE2-115 FPGA board.☆47Updated 8 years ago
- AXI memory-mapped VGA module originally designed for the Avent Zedboard☆15Updated 8 years ago
- verilog CNN generator for FPGA☆34Updated 4 years ago
- ☆105Updated 5 years ago
- HOG + SVM on FPGA☆26Updated 4 years ago
- Image Processing on FPGA using VHDL☆41Updated 10 years ago
- Updated version of the XUP Workshops☆18Updated 6 years ago
- This repository contains all labs done as a part of the Embedded Logic and Design course.☆23Updated 6 years ago
- Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices☆29Updated 9 years ago