shivarajagopal / ece5775-finalLinks
Voice Recognition using FPGA-Based Neural Networks
☆15Updated 9 years ago
Alternatives and similar repositories for ece5775-final
Users that are interested in ece5775-final are comparing it to the libraries listed below
Sorting:
- Adding PR to the PYNQ Overlay☆19Updated 8 years ago
- Scripts to automate the process of building an image for the Xilinx PYNQ project. This repository is deprecated as its functionality is n…☆20Updated 8 years ago
- The objective is to implement a Neural Network in VHDL code. It is aiming the Cyclone II FPGA Starter Development Kit hardware, but the N…☆29Updated 8 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).☆61Updated 3 years ago
- A ZipCPU SoC for the Nexys Video board supporting video functionality☆19Updated last year
- Designing Relocatable FPGA Partitions with Vivado Design Suite☆10Updated 7 years ago
- ☆109Updated 6 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆28Updated 4 years ago
- Zynq PR Management☆13Updated 9 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆63Updated 8 months ago
- Parallel Array of Simple Cores. Multicore processor.☆99Updated 6 years ago
- Networking Overlay on PYNQ☆50Updated 6 years ago
- This repository contains a set of examples of opencl code that can run on the zedboard zynq all programmable soc.☆16Updated 9 years ago
- Python Jupyter Notebooks and FPGA designs showcasing what myHDL can do over traditional Verilog or VHDL☆36Updated 7 years ago
- Repository of HW design and SW for Ultra96 board + MIPI board☆17Updated 6 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆200Updated 7 years ago
- Expiremental Speech Recognition System using VHDL & MATLAB.☆49Updated 7 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- SDSoC platforms for Digilent Zynq boards☆12Updated 8 years ago
- Collection of hardware description languages writings and code snippets☆28Updated 10 years ago
- Python tools for Vivado Projects☆72Updated 6 years ago
- ☆83Updated 5 years ago
- Hot & Spicy tool suite☆23Updated 3 years ago
- Source code of basic Xilinx Vivado HLS image processing tutorial using HLS openCV functions☆26Updated 7 years ago
- Ethernet Mezzanine Card for the Ultra96☆16Updated 2 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 7 years ago
- Verilog language support in Atom☆18Updated 6 years ago
- (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…☆89Updated 7 years ago