Alternatives and similar repositories for educational-materials

Users that are interested in educational-materials are comparing it to the libraries listed below

• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆39Updated 2 years ago
• NJU-ProjectN / am-kernels
  AbstractMachine kernels
  ☆63Updated 2 weeks ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• nkgongxl / ucoreonrv
  ☆50Updated 4 years ago
• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆42Updated 3 years ago
• riscv-and-rust-and-decaf / riscv32i-cpu-chisel
  riscv32i-cpu
  ☆18Updated 4 years ago
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆50Updated 3 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆47Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆40Updated 7 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆61Updated 2 years ago
• lmxyy / Computer-Architecture-Task-2
  Riscv32 CPU Project
  ☆90Updated 7 years ago
• 2horse9sun / ucb_sp20_cs152_lab
  UC Berkeley CS152 Computer Architecture and Engineering Labs
  ☆25Updated 4 years ago
• Ch-EnShen / UCB-CS152-all-materials
  This repository collects all materials from past years of cs152.
  ☆47Updated 10 months ago
• wshenyi / EECS-470-FinalProject
  A 2-Way Super-Scalar OoO RISC-V Core Based on Intel P6 Microarchitecture.
  ☆14Updated 2 years ago
• arch-simulator-sig / advanced-computer-architecture
  体系结构研讨 + ysyx高阶大纲 (WIP
  ☆156Updated 7 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆36Updated 3 years ago
• jiangxincode / CacheSim
  A simulator of Cache
  ☆75Updated 7 months ago
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆135Updated 10 months ago
• adamgallas / MIT_Bluespec_RISCV_Tutorial
  ☆22Updated 2 years ago
• USTC-System-Courses / CECS-Lab
  ☆36Updated last year
• 0xd3ba / build-your-own-prefetcher
  This repository is meant to be a guide for building your own prefetcher for CPU caches and evaluating it, using ChampSim simulator
  ☆35Updated 3 years ago
• MrAMS / verilogModuleAddPrefix
  verilog module add prefix script 可用于ysyx项目添加学号
  ☆13Updated last year
• miaochenlu / Gem5_tutorials
  ☆19Updated last year
• datenlord / training
  ☆10Updated last year
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆30Updated 2 years ago
• gem5bootcamp / gem5-bootcamp-env
  The gem5 Bootcamp 2022 environment. Archived.
  ☆36Updated 10 months ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• NSCSCC-2020-Fudan / FDU1.1-NSCSCC
  复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品
  ☆43Updated 4 years ago
• Maxpicca-Li / CDIM
  CQU Dual Issue Machine
  ☆36Updated 10 months ago