Alternatives and similar repositories for zpu:

Users that are interested in zpu are comparing it to the libraries listed below

• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆209Updated 11 months ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆123Updated 9 years ago
• Arlet / verilog-6502
  A Verilog HDL model of the MOS 6502 CPU
  ☆341Updated 2 years ago
• jamesbowman / j1
  The J1 CPU
  ☆167Updated 4 years ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆305Updated last year
• jamieiles / 80x86
  80186 compatible SystemVerilog CPU core and FPGA reference design
  ☆390Updated last year
• f32c / f32c
  A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz
  ☆413Updated this week
• stnolting / neo430
  A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.
  ☆201Updated 3 years ago
• enjoy-digital / litedram
  Small footprint and configurable DRAM core
  ☆403Updated 3 months ago
• YosysHQ / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆411Updated last week
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆124Updated 7 months ago
• howerj / forth-cpu
  A Forth CPU and System on a Chip, based on the J1, written in VHDL
  ☆344Updated last year
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆310Updated 2 months ago
• YosysHQ / fpga-toolchain
  Multi-platform nightly builds of open source FPGA tools
  ☆295Updated 3 years ago
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆174Updated last month
• jamesbowman / swapforth
  Swapforth is a cross-platform ANS Forth
  ☆288Updated last year
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆156Updated last month
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated last year
• Domipheus / TPU
  TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. De…
  ☆144Updated 8 years ago
• lawrie / fpga_pio
  An attempt to recreate the RP2040 PIO in an FPGA
  ☆295Updated 10 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆270Updated 8 months ago
• 1801BM1 / vm80a
  i8080 precise replica in Verilog, based on reverse engineering of real die
  ☆154Updated 5 years ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆166Updated 4 years ago
• bluespec / Flute
  RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
  ☆366Updated last year
• marmolejo / zet
  Open source implementation of a x86 processor
  ☆320Updated 7 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆134Updated 2 years ago
• emard / ulx3s
  PCB for ULX3S FPGA R&D board
  ☆389Updated last year
• antonblanchard / microwatt
  A tiny Open POWER ISA softcore written in VHDL 2008
  ☆679Updated this week
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆142Updated last year