openhwgroup / cva6-platform
CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
☆11Updated last year
Alternatives and similar repositories for cva6-platform:
Users that are interested in cva6-platform are comparing it to the libraries listed below
- CVA6 SDK containing RISC-V tools and Buildroot☆64Updated 10 months ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆52Updated last week
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆91Updated 3 weeks ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆61Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆71Updated last week
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆50Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 2 months ago
- Pure digital components of a UCIe controller☆61Updated 2 weeks ago
- Advanced Architecture Labs with CVA6☆58Updated last year
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆63Updated 5 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- The OpenPiton Platform☆16Updated 8 months ago
- RISC-V IOMMU Demo (Linux & Bao)☆20Updated last year
- Top project for RISC-V Matrix extension proposal and related opensource implementations.☆30Updated last year
- RISC-V Matrix Specification☆21Updated 4 months ago
- AIA IP compliant with the RISC-V AIA spec☆39Updated 2 months ago
- vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器☆51Updated 5 years ago
- Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)☆55Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 4 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆65Updated 9 months ago
- ☆30Updated 4 months ago
- ☆60Updated 2 months ago
- This repository is dedicated to providing a comprehensive guide and practical examples for using VC Formal for formal verification. Our g…☆26Updated last year
- ☆79Updated last year
- pulp_soc is the core building component of PULP based SoCs☆79Updated last month
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆102Updated 3 weeks ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 10 months ago
- zero-riscy CPU Core☆16Updated 6 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆34Updated last year
- HW Design Collateral for Caliptra RoT IP☆89Updated this week