openhwgroup / cva6-platform
CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
☆10Updated last year
Related projects ⓘ
Alternatives and complementary repositories for cva6-platform
- CVA6 SDK containing RISC-V tools and Buildroot☆61Updated 4 months ago
- IOMMU IP compliant with the RISC-V IOMMU Specification v1.0☆79Updated last week
- PCI Express controller model☆45Updated 2 years ago
- RISC-V IOMMU in verilog☆16Updated 2 years ago
- ☆81Updated 2 years ago
- Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)☆54Updated last year
- AIA IP compliant with the RISC-V AIA spec☆30Updated 2 months ago
- RISC-V IOMMU Specification☆93Updated last month
- RISC-V IOMMU Demo (Linux & Bao)☆15Updated 11 months ago
- RISC-V Matrix Specification☆14Updated 2 months ago
- Setup scripts and files needed to compile CoreMark on RISC-V☆64Updated 3 months ago
- HW Design Collateral for Caliptra RoT IP☆76Updated this week
- A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)☆90Updated last week
- RISC-V Nexus Trace TG documentation and reference code☆44Updated last month
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆27Updated 6 months ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆58Updated last week
- pulp_soc is the core building component of PULP based SoCs☆78Updated 3 months ago
- Converts ELF files to HEX files that are suitable for Verilog's readmemh.☆81Updated 2 years ago
- RISC-V Verification Interface☆74Updated 2 months ago
- Repository containing the guide and code for booting RISC-V full system linux using gem5.☆46Updated 3 years ago
- A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …☆72Updated 2 months ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆42Updated last month
- Proposal for new Embedded ABI (EABI) for use in embedded RISC-V systems.☆26Updated 3 years ago
- ☆55Updated this week
- ☆39Updated 2 years ago
- ☆25Updated 9 months ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆19Updated 7 months ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆60Updated last year
- An OpenRISC 1000 multi-core virtual platform based on SystemC/TLM☆9Updated last year
- A Fast, Low-Overhead On-chip Network☆136Updated 2 weeks ago