Alternatives and similar repositories for cva6-platform

Users that are interested in cva6-platform are comparing it to the libraries listed below

• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆74Updated 3 months ago
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆102Updated last week
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆63Updated 2 years ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆54Updated 4 years ago
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆19Updated 2 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆57Updated last month
• openhwgroup / core-v-polara-apu
  The OpenPiton Platform
  ☆16Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆112Updated this week
• ucb-bar / sha3
  ☆80Updated last year
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆19Updated 2 years ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆70Updated last year
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 11 years ago
• quic / qbox
  Qbox
  ☆59Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆90Updated last month
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated last month
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆65Updated 5 years ago
• machineware-gmbh / vcml
  A modeling library with virtual components for SystemC and TLM simulators
  ☆168Updated this week
• agra-uni-bremen / riscv-vp
  RISC-V Virtual Prototype
  ☆177Updated 9 months ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 7 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆117Updated this week
• poweihuang17 / Documentation_Spike
  Documentation for RISC-V Spike
  ☆103Updated 6 years ago
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆155Updated 4 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆80Updated 6 months ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆89Updated last year
• riscv-ovpsim / imperas-riscv-tests
  ☆189Updated last year
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆137Updated 3 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆66Updated 3 years ago
• arm-university / SoC-design-and-prototyping-Research-Enablement-Kit
  SoC design & prototyping
  ☆14Updated 3 months ago