Alternatives and similar repositories for cva6-platform

Users that are interested in cva6-platform are comparing it to the libraries listed below

• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆75Updated last month
• zero-day-labs / riscv-iommu
  IOMMU IP compliant with the RISC-V IOMMU Specification v1.0
  ☆106Updated last month
• quic / qbox
  Qbox
  ☆70Updated this week
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆115Updated this week
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 4 months ago
• li3tuo4 / rc-fpga-zcu
  Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)
  ☆64Updated 2 years ago
• ppeetteerrs / gem5-RISC-V-FS-Linux
  Repository containing the guide and code for booting RISC-V full system linux using gem5.
  ☆55Updated 4 years ago
• riscvarchive / riscv-CMOs
  ☆89Updated 2 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆124Updated this week
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆92Updated last week
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆63Updated 2 weeks ago
• pulp-platform / culsans
  Tightly-coupled cache coherence unit for CVA6 using the ACE protocol
  ☆37Updated last year
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated 10 months ago
• pulp-platform / pulp_soc
  pulp_soc is the core building component of PULP based SoCs
  ☆81Updated 8 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆112Updated 2 years ago
• Xilinx / pcie-model
  PCI Express controller model
  ☆68Updated 3 years ago
• sld-columbia / esp-caches
  SystemVerilog overhaul of ESP L2 and LLC caches with directory based protocol
  ☆17Updated 8 months ago
• ics-jku / riscv-vp-plusplus
  RISCV-VP++ is a extended and improved successor of the RISC-V based Virtual Prototype (VP) RISC-V VP. It is maintained at the Institute f…
  ☆45Updated last week
• openhwgroup / core-v-polara-apu
  The OpenPiton Platform
  ☆17Updated last year
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆70Updated last year
• freecores / robust_axi_fabric
  Generic AXI interconnect fabric
  ☆13Updated 11 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 2 years ago
• ucb-bar / sha3
  ☆81Updated last year
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated 2 weeks ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆47Updated this week
• Xilinx / systemctlm-cosim-demo
  QEMU libsystemctlm-soc co-simulation demos.
  ☆156Updated 5 months ago
• riscv-boom / riscv-coremark
  Setup scripts and files needed to compile CoreMark on RISC-V
  ☆71Updated last year
• riscv-verification / RVVI
  RISC-V Verification Interface
  ☆119Updated this week
• meton-robean / Vector_MulAdd_Accelerator
  vector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
  ☆54Updated 5 years ago