Alternatives and similar repositories for wiki:

Users that are interested in wiki are comparing it to the libraries listed below

• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 8 months ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆20Updated 2 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆103Updated last month
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 4 years ago
• ryuz / jelly
  Original FPGA platform
  ☆59Updated this week
• liva / xhci_uio
  ☆27Updated 7 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆102Updated 3 years ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago
• atsisy / sloba
  Stacking List Oriented Basic Architecture Allocator
  ☆15Updated 6 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• alphaKAI / cr0cd
  CR0.CD manipulate Linux Kernel Module as a proc filesystem
  ☆19Updated 5 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆52Updated 8 years ago
• susanow / susanow
  Thread based NFVi on DPDK
  ☆26Updated 7 years ago
• aquaxis / synverll
  ☆14Updated 8 years ago
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 4 years ago
• onikiri / onikiri2
  ☆39Updated 6 months ago
• garasubo / T-Visor
  Real-time hypervisor for ARM
  ☆64Updated 8 years ago
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆35Updated 11 years ago
• msyksphinz-self / xv6_translate
  translation of XV6
  ☆49Updated 6 years ago
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆17Updated 7 months ago
• edenden / end.ac
  SRv6 function of multi-tenant proxy by SRH caching over AF_XDP
  ☆22Updated 5 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 2 years ago
• syuu1228 / howto_implement_hypervisor
  Software Design誌の連載「ハイパーバイザの作り方」の原稿公開用リポジトリ
  ☆215Updated 6 years ago
• yasukata / iip
  iip: an integratable TCP/IP stack
  ☆74Updated 2 weeks ago
• diningyo / dirv
  This is my first trial project for designing RISC-V in Chisel
  ☆17Updated 10 months ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆21Updated 4 months ago