Alternatives and similar repositories for synverll

Users that are interested in synverll are comparing it to the libraries listed below

• synthesijer / synthesijer
  ☆52Updated last year
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆107Updated 3 years ago
• PyHDI / PyCoRAM
  Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
  ☆53Updated 8 years ago
• ryuz / jelly
  Original FPGA platform
  ☆68Updated this week
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 5 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆107Updated 7 months ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 4 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• kazuyamashi / cReComp
  ☆13Updated 7 years ago
• vengineer-systemverilog / All-of-SystemVerilog
  みんなのSystemVerilog
  ☆19Updated 3 years ago
• tmatsuya / wiki
  ☆38Updated 8 years ago
• rits-drsl / ZybotR2-96-fpt19
  An UGV-system using SoC-FPGA developed for FPGA design competition held on ICFPT2019
  ☆17Updated 5 years ago
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆46Updated 4 years ago
• akita11 / mklsi
  Design data files for MakeLSI
  ☆11Updated 9 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆162Updated 2 weeks ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆25Updated 2 years ago
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆36Updated 11 years ago
• HirokiNakahara / HLS_FPGA_NES
  An FPGA NES emulator designed by a high level synthesis (HLS)
  ☆17Updated 8 years ago
• onikiri / onikiri2
  ☆39Updated last year
• dtc-work / Qumico
  ☆37Updated 2 years ago
• d-kato / mbed-gr-libs
  Library group for GR-boards.
  ☆12Updated 5 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• ciniml / fpga_samples
  FPGA samples
  ☆23Updated 5 months ago
• ucb-bar / zscale
  Z-scale Microarchitectural Implementation of RV32 ISA
  ☆55Updated 8 years ago
• MakeLSI / OpenRule1um
  Open design rule (1um)
  ☆21Updated 2 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• osafune / peridot
  'PERIDOT' - Simple & Compact FPGA board
  ☆25Updated 9 years ago
• tkat0 / pynqmmult
  "mmult" example using SDSoC for PYNQ board
  ☆11Updated 8 years ago
• fixstars / ultra96_design
  Repository of HW design and SW for Ultra96 board + MIPI board
  ☆17Updated 6 years ago