Alternatives and similar repositories for CPU32:

Users that are interested in CPU32 are comparing it to the libraries listed below

• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆30Updated 6 months ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• msyksphinz-self / xv6_translate
  translation of XV6
  ☆49Updated 6 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆52Updated 4 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 4 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 5 years ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆101Updated 2 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 5 years ago
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated last month
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆44Updated 3 years ago
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆10Updated 5 years ago
• virtualsecureplatform / V2TT
  This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.
  ☆18Updated 4 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆102Updated 2 months ago
• nlsynth / iroha
  Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
  ☆35Updated 3 years ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆28Updated 5 months ago
• peta-okechan / xv6textjp
  xv6のテキスト(book-rev6.pdf)を超適当翻訳してPDF化したもの
  ☆28Updated 11 years ago
• ryuz / jelly
  Original FPGA platform
  ☆54Updated last week
• icf3 / zevios
  original 8bit CPU of ICF3-Z
  ☆11Updated 4 years ago
• joisino / le3hw
  intel を越える
  ☆16Updated 7 years ago
• tmatsuya / wiki
  ☆36Updated 7 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆19Updated 3 months ago
• kamiyaowl / rv32i-sim
  RISC-V Software Simulation
  ☆20Updated 5 years ago
• cpu-dev / cpu-dev.github.io
  ☆15Updated 4 years ago
• msyksphinz-self / swimmer_rust
  RISC-V Simulator written in Rust
  ☆20Updated 4 years ago
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆16Updated 6 months ago
• tanakamura / pllp
  ☆63Updated last year
• hsjoihs / c-compiler
  seccamp2018 c compiler
  ☆53Updated 2 years ago
• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆148Updated 2 months ago
• shioyadan / advanced-computer-organization
  ☆152Updated 4 months ago
• aquaxis / synverll
  ☆14Updated 8 years ago