Alternatives and similar repositories for CPU32

Users that are interested in CPU32 are comparing it to the libraries listed below

• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• msyksphinz-self / xv6_translate
  translation of XV6
  ☆49Updated 7 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 6 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• VLSI-JP / VLSI-JP.github.io
  ☆26Updated last week
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆46Updated 4 years ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated last year
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆107Updated 3 years ago
• horie-t / homemade-riscv
  『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
  ☆13Updated 6 years ago
• shioyadan / advanced-computer-organization
  ☆168Updated last year
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 5 months ago
• msyksphinz-self / support_ca_llvm_book
  ☆142Updated last year
• i4kimura / chip_architect
  Translation of http://chip-architect.com/news/2003_09_21_Detailed_Architecture_of_AMDs_64bit_Core.html
  ☆11Updated 6 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆25Updated 11 months ago
• peta-okechan / xv6textjp
  xv6のテキスト(book-rev6.pdf)を超適当翻訳してPDF化したもの
  ☆28Updated 12 years ago
• tanakamura / pllp
  ☆63Updated 2 years ago
• virtualsecureplatform / V2TT
  This is the repository for the transpiler to compile Verilog to C++ code with TFHE library.
  ☆18Updated 5 years ago
• cpu-dev / cpu-dev.github.io
  ☆16Updated 5 years ago
• msyksphinz-self / swimmer_rust
  RISC-V Simulator written in Rust
  ☆20Updated 5 years ago
• hsjoihs / c-compiler
  seccamp2018 c compiler
  ☆56Updated 3 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆53Updated 3 months ago
• garasubo / embedded-book
  ☆36Updated 4 years ago
• ep2k / epGB
  Game Boy / Game Boy Color emulator running on an FPGA
  ☆18Updated last year
• sozysozbot / 2kmcc
  ☆29Updated 2 years ago
• agehama / Pita
  Constraint geometry processing language
  ☆18Updated 5 years ago
• doraneko94 / sevendayshpc.rs
  WIP: 一週間でなれる！スパコンプログラマ Rust版
  ☆38Updated 4 years ago
• tomoyuki-nakabayashi / book
  The Embedded Rust Bookの和訳レポジトリです
  ☆30Updated 4 years ago
• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆28Updated last year