Alternatives and similar repositories for minispec

Users that are interested in minispec are comparing it to the libraries listed below

• harmonylang / harmony
  A Python-like programming language for testing and experimenting with concurrent programs.
  ☆26Updated last month
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆64Updated last month
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆191Updated this week
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆145Updated last week
• cucapra / turnt
  simple snapshot-style integration testing for commands
  ☆71Updated 3 months ago
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆160Updated 2 months ago
• aappleby / metron
  A C++ to Verilog translation tool with some basic guarantees that your code will work.
  ☆172Updated 6 months ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆37Updated 3 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆52Updated last month
• sifiveinc / wake
  The SiFive wake build tool
  ☆91Updated last week
• rcslab / aurora
  Aurora Single Level Store
  ☆31Updated last year
• pfalcon / ssabook
  Mirror of InriaForge SSABook repository: https://gforge.inria.fr/projects/ssabook/ (was scheduled for retirement at the end of 2020, was …
  ☆142Updated 5 years ago
• OpenMachine-ai / tinyfive
  TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
  ☆62Updated last year
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆95Updated 3 years ago
• os-chip-design / os-chip-design
  ☆23Updated 2 years ago
• jhhuh / tinyemu
  Fabrice Bellard's tinyemu (https://bellard.org/tinyemu/)
  ☆65Updated 3 years ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆85Updated this week
• mwillsey / cs265
  Website for CS 265
  ☆29Updated 8 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆112Updated last week
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 2 years ago
• twizzler-operating-system / twizzler-public
  Public-facing version of the Twizzler OS source code. Note: this is not completely up-to-date with internal Twizzler code.
  ☆65Updated 5 years ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆158Updated last month
• cucapra / diospyros
  Search-based compiler for high-performance DSP programming
  ☆67Updated 10 months ago
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated last month
• P3109 / Public
  materials available to the public
  ☆27Updated last month
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆73Updated 2 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆74Updated 3 weeks ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆161Updated 5 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 3 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago