Alternatives and similar repositories for minispec:

Users that are interested in minispec are comparing it to the libraries listed below

• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆149Updated 2 years ago
• OpenXiangShan / CoupledL2
  Open-source non-blocking L2 cache
  ☆41Updated this week
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆12Updated last month
• chipsalliance / playground
  chipyard in mill :P
  ☆78Updated last year
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 4 years ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆142Updated 9 months ago
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆80Updated 4 months ago
• iscas-tis / riscv-spec-core
  Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.
  ☆13Updated last week
• najaeda / naja-verilog
  A standalone structural (gate-level) verilog parser
  ☆35Updated this week
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆80Updated last week
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆41Updated last week
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆48Updated 8 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆58Updated 3 weeks ago
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆70Updated last year
• IBM / chiffre
  A fault-injection framework using Chisel and FIRRTL
  ☆36Updated 2 years ago
• ucb-bar / shuttle
  A Rocket-based RISC-V superscalar in-order core
  ☆31Updated 2 weeks ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆84Updated last year
• chipsalliance / treadle
  Chisel/Firrtl execution engine
  ☆154Updated 8 months ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• ksco / chibicc-riscv
  A fork of chibicc ported to RISC-V assembly.
  ☆40Updated 2 years ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆60Updated last year
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆61Updated 11 months ago
• ucb-bar / midas
  FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL
  ☆100Updated 5 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆54Updated this week
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆37Updated 3 weeks ago
• hughperkins / cpu-tutorial
  Tutorial on building your own CPU, in Verilog
  ☆33Updated 3 years ago
• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆36Updated 2 years ago
• rsnikhil / ICFP2020_Bluespec_Tutorial
  Tutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
  ☆72Updated 2 years ago
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆160Updated 3 months ago