minispec-hdl / minispecLinks
Minispec Hardware Description Language
☆23Updated last year
Alternatives and similar repositories for minispec
Users that are interested in minispec are comparing it to the libraries listed below
Sorting:
- Working Draft of the RISC-V J Extension Specification☆191Updated 2 weeks ago
- Time-sensitive affine types for predictable hardware generation☆147Updated 2 months ago
- A Python-like programming language for testing and experimenting with concurrent programs.☆32Updated 3 months ago
- A Hardware Pipeline Description Language☆49Updated 5 months ago
- NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.☆76Updated last month
- The SiFive wake build tool☆91Updated this week
- materials available to the public☆29Updated this week
- RISC-V BSV Specification☆23Updated 5 years ago
- Website for CS 265☆33Updated last year
- FPGA Assembly (FASM) Parser and Generator☆99Updated 3 years ago
- UCLID5: formal modeling, verification, and synthesis of computational systems☆153Updated 6 months ago
- CHERI-RISC-V model written in Sail☆66Updated 6 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆117Updated 4 months ago
- Simple demonstration of using the RISC-V Vector extension☆50Updated last year
- The HW-CBMC and EBMC Model Checkers for Verilog☆101Updated this week
- A core language for rule-based hardware design 🦑☆166Updated last month
- RISC-V emulator in python☆63Updated last year
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆181Updated 8 months ago
- CHERI C/C++ Programming Guide☆40Updated this week
- A standalone structural (gate-level) verilog parser☆40Updated 3 weeks ago
- FPGA synthesis tool powered by program synthesis☆54Updated 3 weeks ago
- The specification for the FIRRTL language☆62Updated last month
- RiscyOO: RISC-V Out-of-Order Processor☆169Updated 5 years ago
- Lipsi: Probably the Smallest Processor in the World☆89Updated last year
- ☆306Updated this week
- A teaching-focused RISC-V CPU design used at UC Davis☆152Updated 2 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆87Updated 3 months ago
- TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems☆162Updated 3 years ago
- RISC-V Formal Verification Framework☆175Updated this week
- ☆70Updated last year