Alternatives and similar repositories for minispec

Users that are interested in minispec are comparing it to the libraries listed below

• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆193Updated last month
• harmonylang / harmony
  A Python-like programming language for testing and experimenting with concurrent programs.
  ☆32Updated 3 months ago
• cucapra / dahlia
  Time-sensitive affine types for predictable hardware generation
  ☆148Updated 3 weeks ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆49Updated 6 months ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆54Updated last month
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆66Updated 6 months ago
• sifiveinc / wake
  The SiFive wake build tool
  ☆92Updated this week
• najaeda / naja-verilog
  A standalone structural (gate-level) verilog parser
  ☆40Updated this week
• AntonLydike / riscemu
  RISC-V emulator in python
  ☆63Updated last year
• pydrofoil / pydrofoil
  A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one
  ☆82Updated this week
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• mit-plv / koika
  A core language for rule-based hardware design 🦑
  ☆170Updated last month
• P3109 / Public
  materials available to the public
  ☆29Updated last week
• OpenMachine-ai / tinyfive
  TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples
  ☆71Updated 2 years ago
• aappleby / metron
  A C++ to Verilog translation tool with some basic guarantees that your code will work.
  ☆176Updated 11 months ago
• chipsalliance / t1
  ☆309Updated this week
• microsoft / kanagawa
  High level synthesis language for hardware design
  ☆81Updated last month
• mwillsey / cs265
  Website for CS 265
  ☆33Updated last year
• firesim / FireMarshal
  Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
  ☆87Updated 3 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆119Updated 5 months ago
• cucapra / filament
  Fearless hardware design
  ☆187Updated 5 months ago
• diffblue / hw-cbmc
  The HW-CBMC and EBMC Model Checkers for Verilog
  ☆101Updated this week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆26Updated 2 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆23Updated 6 years ago
• adamwalker / fpga-kvs
  A networked FPGA key-value store written in Clash
  ☆30Updated last year
• uclid-org / uclid
  UCLID5: formal modeling, verification, and synthesis of computational systems
  ☆154Updated 6 months ago
• kvakil / venus
  RISC-V instruction set simulator built for education
  ☆221Updated 3 years ago
• CTSRD-CHERI / qemu
  QEMU with support for CHERI
  ☆63Updated 3 weeks ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆62Updated 3 weeks ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆153Updated 2 years ago