minispec-hdl / minispecLinks
Minispec Hardware Description Language
☆21Updated last year
Alternatives and similar repositories for minispec
Users that are interested in minispec are comparing it to the libraries listed below
Sorting:
- A Hardware Pipeline Description Language☆45Updated last year
- FPGA synthesis tool powered by program synthesis☆49Updated last month
- materials available to the public☆25Updated 7 months ago
- A core language for rule-based hardware design 🦑☆156Updated 2 weeks ago
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆27Updated 4 years ago
- Time-sensitive affine types for predictable hardware generation☆143Updated 11 months ago
- A RISC-V Core (RV32I) written in Chisel HDL☆103Updated 2 months ago
- A fork of chibicc ported to RISC-V assembly.☆40Updated 3 years ago
- A teaching-focused RISC-V CPU design used at UC Davis☆148Updated 2 years ago
- Manythread RISC-V overlay for FPGA clusters☆38Updated 2 years ago
- A simple, easily extendable, RISCV assembler for the RV32I subset in Python.☆28Updated last year
- GL0AM GPU Accelerated Gate Level Logic Simulator☆18Updated 2 weeks ago
- The ISA specification for the ZiCondOps extension.☆19Updated last year
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆27Updated 11 years ago
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆66Updated 2 months ago
- A basic working RISCV emulator written in C☆69Updated last year
- RISC-V BSV Specification☆20Updated 5 years ago
- Dual-issue RV64IM processor for fun & learning☆60Updated last year
- RiscyOO: RISC-V Out-of-Order Processor☆158Updated 4 years ago
- chipyard in mill :P☆78Updated last year
- CHERI-RISC-V model written in Sail☆60Updated last week
- An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …☆46Updated 10 months ago
- TinyFive is a lightweight RISC-V emulator and assembler written in Python with neural network examples☆62Updated last year
- The specification for the FIRRTL language☆58Updated last week
- RISC-V Formal Verification Framework☆141Updated 2 weeks ago
- Open-source non-blocking L2 cache☆43Updated this week
- Working Draft of the RISC-V J Extension Specification☆187Updated last month
- A standalone structural (gate-level) verilog parser☆36Updated last month
- A tool for synthesizing Verilog programs☆93Updated this week
- The code for the RISC-V from scratch blog post series.☆91Updated 4 years ago