A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
☆162May 20, 2022Updated 3 years ago
Alternatives and similar repositories for MIPS-pipeline-processor
Users that are interested in MIPS-pipeline-processor are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆140Apr 3, 2020Updated 6 years ago
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆60Jan 28, 2025Updated last year
- 💻 A 5-stage pipeline MIPS CPU implementation in Verilog.☆34Jul 5, 2020Updated 5 years ago
- ☆18Aug 8, 2017Updated 8 years ago
- Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu☆25Jun 5, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Nov 28, 2019Updated 6 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆22Oct 9, 2019Updated 6 years ago
- This project give overview of RTL to GDSII of universal shift register using OpenLane and Skywater130 PDK. OpenLane is an automated open-…☆11Jul 19, 2022Updated 3 years ago
- A classic 5-stage pipeline MIPS 32-bit processor, including a 2-bit branch predictor, a branch prediction buffer and a direct-mapped cach…☆76Nov 4, 2024Updated last year
- An 8 input interrupt controller written in Verilog.☆28Mar 22, 2012Updated 14 years ago
- 5 stage pipelined MIPS-32 processor☆57Apr 20, 2020Updated 5 years ago
- Memory Compiler Tutorial☆13Aug 2, 2022Updated 3 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆18Sep 2, 2023Updated 2 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- APB Timer Unit☆14Oct 30, 2025Updated 5 months ago
- Course project of Computer Architecture, designed by single-cycle datapath. The verilog code could be completely compiled by Quartus II.☆29Feb 14, 2021Updated 5 years ago
- MIPS CPU implemented in Verilog☆645Oct 3, 2017Updated 8 years ago
- General Purpose IO with APB4 interface☆16May 10, 2024Updated last year
- AHB Bus lite v3.0☆17Aug 7, 2019Updated 6 years ago
- Verilog implementation of various types of CPUs☆77Sep 27, 2019Updated 6 years ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- Parameterized Booth Multiplier in Verilog 2001☆51Oct 30, 2022Updated 3 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆16Apr 12, 2020Updated 6 years ago
- DMA Hardware Description with Verilog☆19Dec 20, 2019Updated 6 years ago
- Simulation of the classic Pacman arcade game on a PanoLogic thin client.☆34Nov 3, 2019Updated 6 years ago
- Design consists of a 32-bit MIPS superscalar pipeline processor in functional Verilog. Runs a cache based memory system, a branch predict…☆15Oct 9, 2017Updated 8 years ago
- DSP WishBone Compatible Cores☆14Jul 17, 2014Updated 11 years ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆10Aug 6, 2025Updated 8 months ago
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 7 years ago
- Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.☆40May 10, 2019Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆35Mar 21, 2020Updated 6 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- Pipelined MIPS architecture created in Verilog. Includes data forwarding and hazard detection.☆16Apr 1, 2018Updated 8 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- This repo is for Edge Vision SoC framework, which facilitates quick porting of users' design for Edge AI and Vision solutions.☆28Feb 13, 2026Updated 2 months ago
- This repository showcases an FPGA-based adaptive noise cancellation system developed for mobile communication applications. Implemented o…☆15Dec 15, 2024Updated last year
- RISC-V RV32I CPU written in verilog☆10Jul 11, 2020Updated 5 years ago
- DSP University Project - Matlab, Simulations, and Verilog Files☆14Jan 14, 2020Updated 6 years ago
- 本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。☆27Jun 1, 2023Updated 2 years ago