mhyousefi / MIPS-pipeline-processor
A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding
☆152Updated 2 years ago
Alternatives and similar repositories for MIPS-pipeline-processor:
Users that are interested in MIPS-pipeline-processor are comparing it to the libraries listed below
- A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall☆38Updated last month
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆120Updated 4 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆107Updated last year
- This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…☆176Updated 7 months ago
- ☆26Updated 10 months ago
- implement convolution neural network on FPGA based on VHDL design☆20Updated 3 years ago
- ECE 3300 HDL Code☆44Updated 2 years ago
- Verilog/SystemVerilog Guide☆61Updated last year
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆38Updated 7 months ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆90Updated 2 years ago
- DDR2 memory controller written in Verilog☆73Updated 13 years ago
- ☆9Updated 11 months ago
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆623Updated 3 months ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆123Updated 5 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆142Updated 8 months ago
- Image Processing Toolbox in Verilog using Basys3 FPGA☆189Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆54Updated 2 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆80Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆133Updated last week
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆116Updated 3 years ago
- Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder☆109Updated 12 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- Various caches written in Verilog-HDL☆115Updated 9 years ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆307Updated 5 months ago
- RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.☆257Updated 7 years ago
- Some useful documents of Synopsys☆65Updated 3 years ago