Alternatives and similar repositories for MIPS-pipeline-processor

Users that are interested in MIPS-pipeline-processor are comparing it to the libraries listed below

• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆141Updated 6 years ago
• neelkshah / MIPS-Processor
  5-stage pipelined 32-bit MIPS microprocessor in Verilog
  ☆137Updated 5 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆166Updated last year
• maze1377 / pipeline-mips-verilog
  A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
  ☆56Updated 10 months ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• merldsu / RISCV_Pipeline_Core
  This repository contains the design files of RISC-V Pipeline Core
  ☆58Updated 2 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆126Updated 3 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆150Updated 9 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆92Updated 4 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆185Updated 3 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆195Updated 3 months ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• raulbehl / 100DaysOfRTL
  100 Days of RTL
  ☆403Updated last year
• lowRISC / style-guides
  lowRISC Style Guides
  ☆472Updated last month
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆37Updated 8 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆71Updated 3 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆56Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆251Updated this week
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆97Updated 6 years ago
• akilm / FPU-IEEE-754
  Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…
  ☆66Updated last year
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆75Updated last year
• wuzeyou / Multiplier16X16
  Classic Booth Code, Wallace Tree, and SquareRoot Carry Select Adder
  ☆121Updated 12 years ago
• x-heep / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆232Updated this week
• bol-edu / caravel-soc_fpga-lab
  ☆19Updated 8 months ago
• abdelazeem201 / Cadence-RTL-to-GDSII-Flow
  In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
  ☆98Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆140Updated 7 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆183Updated last year
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆224Updated last month