Alternatives and similar repositories for MIPS-pipeline-processor

Users that are interested in MIPS-pipeline-processor are comparing it to the libraries listed below

• maze1377 / pipeline-mips-verilog
  A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
  ☆50Updated 5 months ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆101Updated 2 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆132Updated 5 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆159Updated 2 months ago
• os-fpga / Virtual-FPGA-Lab
  This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, unde…
  ☆204Updated last month
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆132Updated last year
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆50Updated last year
• neelkshah / MIPS-Processor
  5-stage pipelined 32-bit MIPS microprocessor in Verilog
  ☆129Updated 5 years ago
• Caskman / MIPS-Processor-in-Verilog
  Processor repo
  ☆52Updated 11 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆295Updated 7 years ago
• karimmahmoud22 / SystemVerilog-For-Verification
  ☆33Updated last year
• pengwubj / hw_interview_questions
  A collection of commonly asked RTL design interview questions
  ☆31Updated 8 years ago
• cepdnaclk / e16-co502-RV32IM-pipeline-implementation-group1
  The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…
  ☆27Updated 3 years ago
• bol-edu / caravel-soc_fpga-lab
  ☆18Updated 3 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆87Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆104Updated 2 months ago
• ARC-Lab-UF / intel-training-modules
  ☆42Updated 2 years ago
• mitshine / UVM-and-System-Verilog-Manual
  UVM and System Verilog Manuals
  ☆43Updated 6 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated last month
• Buddhimah / System-Bus-Design-Verilog
  This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
  ☆32Updated 5 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆99Updated last year
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆62Updated 2 years ago
• FPGADude / Digital-Design
  Verilog HDL files
  ☆146Updated last year
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆77Updated 13 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆441Updated last month
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆68Updated last year
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆142Updated 9 years ago
• rpjayaraman / DV-resource
  A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.
  ☆19Updated last month
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆126Updated 7 years ago