Alternatives and similar repositories for Real-Time-Image-Video-Dehazing

Users that are interested in Real-Time-Image-Video-Dehazing are comparing it to the libraries listed below

• suisuisi / FPGAandImage
  image processing based FPGA
  ☆109Updated 3 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• nicyyyy / FPGA-CLAHE
  Constrast limited adaptive histogram equlization based on Verilog
  ☆33Updated last year
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆150Updated last year
• DOUDIU / Hardware-Implementation-of-the-Dark-Channel-Prior-Haze-Removal-Algorithm
  The Dark Channel Prior technique is implemented on FPGA using only Verilog code and no Intellectual Property, making it convenient to rep…
  ☆40Updated last year
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆33Updated 3 years ago
• suisuisi / FPGA
  FPGA
  ☆125Updated 5 years ago
• BambooWhispering / FPGA-image-simulation
  FPGA图像处理仿真平台
  ☆26Updated 3 years ago
• bxinquan / zynqmp_cam_isp_demo
  ISP-Lite, VIP, MIPI-RX IP实现，测试平台为KV260+AR1335 3MP@30fps
  ☆98Updated 2 years ago
• AugustinJose1221 / FPGA-Build
  A novel architectural design for stitching video streams in real-time on an FPGA.
  ☆123Updated 3 years ago
• bxinquan / zynq_cam_isp_demo
  基于verilog实现了ISP图像处理IP
  ☆279Updated 2 years ago
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆36Updated 4 years ago
• freecores / jpegencode
  JPEG Encoder Verilog
  ☆76Updated 2 years ago
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆206Updated last month
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆129Updated last year
• luyixdu / ZYNQ_ov5640_hdmi_frame_difference
  帧差法运动目标检测，基于ZYNQ7020
  ☆69Updated 4 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆37Updated 4 years ago
• VVicer / anlu-EG-ISP
  基于安路开发板的bayer视频简单处理
  ☆17Updated 11 months ago
• iyue-zhao / FPGA
  ISP
  ☆12Updated last year
• iharbour-heyaonan / FPGA_image_process
  FPGA实现简单的图像处理算法
  ☆47Updated 2 years ago
• Frogwells / fpga_design
  这是我所开发的两个项目，包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统
  ☆93Updated 7 years ago
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆150Updated 4 years ago
• eepro-bt / documents
  文档编写
  ☆13Updated 4 years ago
• WangXuan95 / FPGA-QOI
  An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。
  ☆29Updated 9 months ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆60Updated 6 years ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆58Updated 5 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆122Updated 6 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆34Updated 5 years ago
• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆16Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆94Updated 5 years ago