kailiuXD / xdcom

Related projects ⓘ

Alternatives and complementary repositories for xdcom

• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆14Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆45Updated 4 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆22Updated 5 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆29Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆29Updated 6 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆35Updated 7 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 7 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆28Updated 2 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆15Updated 10 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆19Updated 5 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆26Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆31Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆45Updated 3 years ago
• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 4 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆25Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆33Updated 9 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆33Updated 2 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆50Updated 10 years ago
• jdocampom / JPEG-Decoder
  Verilog Code for a JPEG Decoder
  ☆31Updated 6 years ago
• wanderingnail / AXI_DMA
  ☆16Updated last year
• lulinchen / jpeg2000_open
  A simple JPEG2000 hardware encoder
  ☆15Updated 4 years ago
• brown9804 / PCIe_physical_layer
  Implementation of the PCIe physical layer
  ☆29Updated 4 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆21Updated 3 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆15Updated 7 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆20Updated 5 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆29Updated 2 years ago
• makararasi / UVM_AXI4-Stream
  ☆12Updated 2 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆13Updated 6 years ago