This is a demo for still image compression application
☆15Apr 14, 2018Updated 8 years ago
Alternatives and similar repositories for xdcom
Users that are interested in xdcom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A simple JPEG2000 hardware encoder☆29Sep 29, 2020Updated 5 years ago
- JPEG2000 compression coder on Xilinx Virtex 5 FPGA☆20Jul 17, 2013Updated 13 years ago
- Image processing on FPGA using verilog☆26Dec 5, 2022Updated 3 years ago
- ☆14Dec 17, 2015Updated 10 years ago
- ☆16Apr 7, 2026Updated 3 months ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- This is a myhdl test environment for the open-cores jpeg_encoder.☆19Oct 23, 2016Updated 9 years ago
- JPEG Encoder Verilog☆83Oct 31, 2022Updated 3 years ago
- implementing a Recurrent Neural Network with binarized weight format on FPGA☆22Sep 3, 2017Updated 8 years ago
- ☆19Sep 12, 2022Updated 3 years ago
- Knowledge Graph of FPGA☆14Aug 21, 2021Updated 4 years ago
- Verilog FPGA code : including experimental DSP audio processor☆14Dec 1, 2020Updated 5 years ago
- FIR,FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. …☆15Jan 19, 2018Updated 8 years ago
- The TV80 (Verilog) synthesizable soft core of Zilog Z80 (forked from http://opencores.org/project,tv80)☆10Jan 9, 2016Updated 10 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- An FPGA-based JPEG-LS encoder, which provides lossless and near-lossless image compression with high compression ratios. 基于FPGA的JPEG-LS编码…☆334Sep 18, 2024Updated last year
- ☆13May 22, 2015Updated 11 years ago
- rubik's cube kocimeba solution implement☆16Aug 5, 2023Updated 2 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 9 years ago
- Unit testing for cocotb☆11Aug 6, 2023Updated 2 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 6 years ago
- Joker TV (USB) FPGA verilog/vhdl code☆16May 19, 2026Updated 2 months ago
- Transmission of HDMI Signals over Spartan 6 - XC6SLX45 . Transmission of High-Definition Multimedia Interface (HDMI) and Digital Visual …☆13Feb 13, 2020Updated 6 years ago
- A soft multimedia/graphics processor prototype in Chisel 3☆11May 3, 2023Updated 3 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- Zedboard projects☆11May 15, 2016Updated 10 years ago
- Example of Python and PyTest powered workflow for a HDL simulation☆15Jan 17, 2021Updated 5 years ago
- Orignal code/dev history for Menshen paper (NSDI 2022), see https://github.com/multitenancy-project/menshen for official version.☆32Apr 26, 2022Updated 4 years ago
- achieve softmax in PYNQ with heterogeneous computing.☆67Nov 1, 2018Updated 7 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Dec 8, 2017Updated 8 years ago
- ☆15Dec 1, 2022Updated 3 years ago
- Language for simplifying parameterized RTL design☆14Apr 3, 2026Updated 3 months ago
- A project demonstrate how to config ad9361 to TX mode and how to transmit GMSK☆17Dec 9, 2018Updated 7 years ago
- Display Stream Compression 1.2a☆16Oct 18, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Jul 21, 2017Updated 9 years ago
- Image Signal Processing Assignments☆16May 1, 2018Updated 8 years ago
- This is a tool to login qq zone using python, with multithreads to scrapy what you want,such as, message, blogs board, and photos.☆10May 11, 2017Updated 9 years ago
- Library of generic verilog buildingblocks☆17Dec 25, 2025Updated 6 months ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- FreeRTOS/lwIP (XAPP1026) for Xilinx Zynq devices using Vivado 2016.1. This port is compatible with Xilinx Vivado 2016.1 and was tested on…☆16Mar 28, 2017Updated 9 years ago
- Translates the DSD/DSF file into WAV file written in C for learning,☆11Feb 21, 2019Updated 7 years ago