kailiuXD / xdcom
This is a demo for still image compression application
☆12Updated 6 years ago
Related projects ⓘ
Alternatives and complementary repositories for xdcom
- Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.☆14Updated 4 years ago
- A simple JPEG2000 hardware encoder☆16Updated 4 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆46Updated 4 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆35Updated 7 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆15Updated 10 years ago
- AHB DMA 32 / 64 bits☆50Updated 10 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆20Updated 5 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆17Updated 6 years ago
- 视频旋转(2019FPGA大赛)☆29Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆41Updated 6 months ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- AXI Interconnect☆46Updated 3 years ago
- ☆34Updated 9 years ago
- A 32 point radix-2 FFT module written in Verilog☆20Updated 4 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆29Updated 2 years ago
- Convolutional Neural Network Implemented in Verilog for System on Chip☆23Updated 5 years ago
- ☆28Updated 4 years ago
- fpga i2c slave verilog hdl rtl☆11Updated 8 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆16Updated 7 years ago
- Interface Protocol in Verilog☆47Updated 5 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆29Updated 2 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆43Updated 3 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆14Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆29Updated 6 years ago
- ☆16Updated 2 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆30Updated 4 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- ☆21Updated 3 years ago
- ☆33Updated 2 years ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆40Updated 5 years ago