Alternatives and similar repositories for xdcom

Users that are interested in xdcom are comparing it to the libraries listed below

• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆50Updated 3 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• freecores / apbi2c
  APB to I2C
  ☆42Updated 11 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆56Updated 3 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• jessepalomera / 10G_EthernetMAC_SystemVerilog_OOP
  Final Project for my course in Advanced Verification with SystemVerilog OOP
  ☆21Updated 3 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆37Updated 4 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆16Updated 4 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆45Updated last week
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆36Updated 3 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆79Updated last year
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆33Updated 3 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆58Updated 8 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆29Updated 4 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆25Updated 8 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆39Updated 2 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆33Updated 5 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆35Updated 3 years ago