Alternatives and similar repositories for CacheSim:

Users that are interested in CacheSim are comparing it to the libraries listed below

• qiyancos / gem5-with-chinese-comment
  Gem5 with chinese comment and introduction (master) and some other std gem5 version.
  ☆41Updated 3 years ago
• quyifei23 / gem5-for-CXL
  this is a repository based on gem5 and aims to be modified for CXL
  ☆21Updated last year
• nicolaswilde / UCAS-Advanced-Computer-Architecture-OpenROAD-flow
  中国科学院大学高级计算机体系结构课程作业：使用OpenROAD-flow完成RTL到GDS全流程
  ☆24Updated 4 years ago
• nkgongxl / ucoreonrv
  ☆50Updated 4 years ago
• cry-daniel / Computer-Architecture-Learning
  ☆58Updated 2 years ago
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆46Updated last year
• FDUCSLG / ICS-2021Spring-FDU
  Introduction to Computer Systems (II), Spring 2021
  ☆49Updated 3 years ago
• kazutoiris / MIT6.175
  MIT6.175 & MIT6.375 Study Notes
  ☆33Updated last year
• nscscc2019ucas / nscscc2019ucas
  ☆34Updated 5 years ago
• lshpku / gem5-fs-handbook
  gem5 FS模式实验手册
  ☆33Updated last year
• SocialistDalao / UltraMIPS_NSCSCC
  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.
  ☆122Updated 8 months ago
• huang-jl / LLCL-MIPS
  LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…
  ☆34Updated 3 years ago
• lshpku / hwd-prefetch-study
  A Study of the SiFive Inclusive L2 Cache
  ☆58Updated last year
• OpenXiangShan / GEM5
  ☆74Updated this week
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 8 months ago
• zencove-thu / zencove-zoom
  Highly configurable out-of-order MIPS32 processor, capable of booting Linux.
  ☆38Updated last year
• PKUZHOU / NeoMem-MICRO-2024
  The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
  ☆43Updated 6 months ago
• yuhanzhu612 / OSCPU
  我的一生一芯项目
  ☆16Updated 3 years ago
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆39Updated 6 years ago
• Quangmire / ChampSim
  ChampSim repository
  ☆28Updated this week
• FCAS-LAB / Chiplet-Gem5-SharedMemory
  ☆27Updated 8 months ago
• pinchenjohnny / Distributed_System_Architecture
  高级计算机体系结构2020，吴俊敏老师，中科大研究生课程
  ☆61Updated last year
• Lyncien / RISC-V-32I
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆72Updated 5 years ago
• 2horse9sun / ucb_sp20_cs152_lab
  UC Berkeley CS152 Computer Architecture and Engineering Labs
  ☆23Updated 4 years ago
• agusnt / Berti-Artifact
  An artifact for Berti: an Accurate and Timely Local-Delta Data Prefetcher
  ☆28Updated 2 years ago
• Shuiliusheng / spec2006_simpoint
  use two version gem5 to create spec2006 cpu simpoint & checkpoint
  ☆15Updated 5 years ago
• gem5 / gem5-resources
  The official repository for the gem5 resources sources.
  ☆63Updated 2 weeks ago
• likmin / ics2019
  南京大学nemu，基于riscv32架构，目前进度PA3
  ☆20Updated 4 years ago