CMU-SAFARI / Sibyl
Source code for the software implementation of Sibyl proposed in our ISCA 2022 paper: Gagandeep Singh et. al., "Sibyl: Adaptive and Extensible Data Placement in Hybrid Storage Systems using Online Reinforcement Learning" at https://people.inf.ethz.ch/omutlu/pub/Sibyl_RL-based-data-placement-in-hybrid-storage-systems_isca22.pdf
☆34Updated 2 years ago
Alternatives and similar repositories for Sibyl:
Users that are interested in Sibyl are comparing it to the libraries listed below
- This is the respository that holds the artifacts of MICRO'23 -- Demystifying CXL Memory with True CXL-Ready Systems and CXL Memory Device…☆44Updated last year
- This is an read-only mirror of the gem5 simulator. The upstream repository is stored in https://gem5.googlesource.com, code reviews shoul…☆34Updated 8 months ago
- ☆68Updated last year
- ☆29Updated 4 years ago
- CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator Based on gem5☆59Updated 3 weeks ago
- ☆94Updated last year
- Simulation infrastructure and validation of Cori☆13Updated 2 years ago
- SmartSSD related benchmarks and toy applications☆8Updated last year
- The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering☆43Updated 7 months ago
- Clio, ASPLOS'22.☆72Updated 3 years ago
- ☆24Updated last year
- CXLMemSim: A pure software simulated CXL.mem for performance characterization☆146Updated 2 weeks ago
- An FPGA-based full-stack in-storage computing system.☆37Updated 4 years ago
- The Artifact Evaluation Version of SOSP Paper #19☆45Updated 7 months ago
- OSDI'24 Nomad implementation☆43Updated 3 months ago
- ☆36Updated last year
- Artifacts of EuroSys'24 paper "Exploring Performance and Cost Optimization with ASIC-Based CXL Memory"☆23Updated last year
- VANS: A validated NVRAM simulator☆26Updated last year
- ☆15Updated 2 years ago
- Tiered memory management☆74Updated 6 months ago
- Exploring the Design Space of Page Management for Multi-Tiered Memory Systems (USENIX ATC '21)☆45Updated 2 years ago
- Sources for the Multi-Clock system as described in the paper: MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems, HPCA 2022.☆19Updated 2 years ago
- CXL Memory Resource Kit top-level repository☆50Updated 2 years ago
- gem5-nvmain hybrid simulator supporting simulation of DRAM-NVM hybrid memory system☆76Updated 5 years ago
- Modifications to GEM5 for running kernel bypass networking. (DPDK)☆15Updated last year
- this is a repository based on gem5 and aims to be modified for CXL☆21Updated last year
- TeRM: Extending RDMA-Attached Memory with SSD [FAST'24]☆40Updated 4 months ago
- ☆12Updated 7 months ago
- A high-performance file system for multicore CPUs and flash storage☆33Updated last year