jatinmandav / Verilog-HDLLinks
Programs based on Verilog - Hardware Description Language
☆8Updated 7 years ago
Alternatives and similar repositories for Verilog-HDL
Users that are interested in Verilog-HDL are comparing it to the libraries listed below
Sorting:
- ☆19Updated last year
- CMake based hardware build system☆29Updated last week
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆15Updated 2 years ago
- Hardware Formal Verification☆15Updated 4 years ago
- Routing Visualization for Physical Design☆19Updated 6 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆12Updated 2 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆13Updated 3 weeks ago
- YosysHQ SVA AXI Properties☆41Updated 2 years ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆37Updated 3 weeks ago
- A configurable SRAM generator☆53Updated last week
- Library of open source Process Design Kits (PDKs)☆48Updated 3 weeks ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- Collection of test cases for Yosys☆18Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- RTLMeter benchmark suite☆20Updated last week
- An open source PDK using TIGFET 10nm devices.☆49Updated 2 years ago
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- An automatic clock gating utility☆50Updated 3 months ago
- design and verification of asynchronous circuits☆38Updated last week
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- sram/rram/mram.. compiler☆35Updated last year
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- OpenDesign Flow Database☆16Updated 6 years ago
- A library and command-line tool for querying a Verilog netlist.☆27Updated 3 years ago
- ☆37Updated 3 years ago
- Digital Standard Cells based SAR ADC☆14Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 5 months ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- A LEF/DEF Utility.☆31Updated 5 years ago