intel / FPGA-Devcloud
Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
☆120Updated last year
Alternatives and similar repositories for FPGA-Devcloud:
Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below
- Tutorials on HLS Design☆51Updated 5 years ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 3 months ago
- ☆286Updated last week
- ☆118Updated 3 years ago
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆47Updated 9 months ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆267Updated 2 weeks ago
- Board files to build Ultra 96 PYNQ image☆154Updated 4 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆101Updated last year
- Learn systemC with examples☆109Updated 2 years ago
- ☆125Updated 5 months ago
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆68Updated 8 months ago
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆369Updated this week
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆207Updated last year
- SDAccel Development Environment Tutorials☆108Updated 5 years ago
- [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.☆122Updated 2 years ago
- This store contains Configurable Example Designs.☆44Updated this week
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆103Updated this week
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆123Updated 2 years ago
- Rosetta: A Realistic High-level Synthesis Benchmark Suite for Software Programmable FPGAs☆164Updated last year
- Brief SystemC getting started tutorial☆88Updated 6 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆82Updated 7 months ago
- ☆200Updated last week
- Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".☆199Updated 3 years ago
- Build Customized FPGA Implementations for Vivado☆315Updated this week
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆102Updated 5 years ago
- Verilog Content Addressable Memory Module☆104Updated 3 years ago
- This repo contains the Limago code☆83Updated last week
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆318Updated 3 months ago
- FOS - FPGA Operating System☆66Updated 4 years ago