intel / FPGA-Devcloud

Related projects ⓘ

Alternatives and complementary repositories for FPGA-Devcloud

• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆46Updated 3 months ago
• Xilinx / Vitis-In-Depth-Tutorial
  ☆116Updated 3 years ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆116Updated this week
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆48Updated last year
• MakarenaLabs / Xilinx-FPGA-HLS-PYNQ-ALVEO-Flow
  Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.
  ☆25Updated 4 years ago
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆103Updated 4 months ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆64Updated 2 months ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆95Updated last year
• Xilinx / Vivado-Design-Tutorials
  ☆160Updated this week
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆92Updated 3 months ago
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆94Updated this week
• pnnl / OpenCGRA
  OpenCGRA is an open-source framework for modeling, testing, and evaluating CGRAs.
  ☆135Updated last year
• hlslibs / hls_tutorials
  Tutorials on HLS Design
  ☆49Updated 4 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆184Updated 6 months ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆260Updated 3 weeks ago
• FPGA-Research-Manchester / fos
  FOS - FPGA Operating System
  ☆62Updated 4 years ago
• UCLA-VAST / AutoBridge
  [FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.
  ☆121Updated last year
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆42Updated this week
• intel / fpga-training
  ☆33Updated 2 months ago
• spcl / hls_tutorial_examples
  Examples shown as part of the tutorial "Productive parallel programming on FPGA with high-level synthesis".
  ☆192Updated 3 years ago
• fpga-opencl-benchmarks / rodinia_fpga
  Rodinia Benchmark Suite for OpenCL-based FPGAs
  ☆30Updated last year
• dcblack / ModernSystemC
  Example code for Modern SystemC using Modern C++
  ☆58Updated 2 years ago
• Xilinx / logicnets
  ☆83Updated 5 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆60Updated this week
• riscv-stc / riscv-matrix-project
  Top project for RISC-V Matrix extension proposal and related opensource implementations.
  ☆23Updated 7 months ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆22Updated 3 months ago
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆152Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆303Updated 6 months ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆137Updated 3 months ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆87Updated 6 months ago