Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
☆123Jul 17, 2023Updated 3 years ago
Alternatives and similar repositories for FPGA-Devcloud
Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆57May 28, 2023Updated 3 years ago
- SYCL-based 2D Stencil Simulation Framework☆18May 3, 2026Updated 4 months ago
- Intel® FPGA Runtime for OpenCL™ Software Technology☆36Feb 25, 2025Updated last year
- ☆35Sep 10, 2024Updated 2 years ago
- BLAS implementation for Intel FPGA☆79Nov 18, 2020Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Quartus Lite docker☆38Sep 26, 2020Updated 5 years ago
- ☆13Aug 22, 2022Updated 4 years ago
- ☆139Aug 31, 2026Updated 2 weeks ago
- ☆18Jul 3, 2025Updated last year
- Simulated Annealing for MAX-CUT problems on {+1,-1}-weighted complete graphs☆12Feb 2, 2019Updated 7 years ago
- Student starter code for Fall 2019 labs☆13Nov 28, 2019Updated 6 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 9 years ago
- Vitis_Accel_Examples☆605Aug 31, 2026Updated 2 weeks ago
- C++ template meta-programmable framework for authoring Pintools☆37Apr 1, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆22Aug 31, 2022Updated 4 years ago
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 6 years ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆93Mar 9, 2026Updated 6 months ago
- Open Programmable Acceleration Engine☆270Jul 10, 2026Updated 2 months ago
- ☆810Jul 13, 2026Updated 2 months ago
- Install Intel FPGA 'Quartus Prime' software on remote servers☆65Feb 14, 2025Updated last year
- SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM☆124Nov 4, 2024Updated last year
- RISC-V Integrated Matrix Development Repository☆26Aug 24, 2026Updated 3 weeks ago
- ☆26Feb 15, 2025Updated last year
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- SystemVerilog Tutorial☆238Mar 7, 2026Updated 6 months ago
- Implementation of a cache memory in verilog☆14Dec 5, 2017Updated 8 years ago
- Samples for Intel® oneAPI Toolkits☆1,161Jul 28, 2026Updated last month
- Log file scanner used with EDA tools to classify errors and warnings☆13Nov 14, 2022Updated 3 years ago
- ☆10Jul 5, 2025Updated last year
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆342Jan 20, 2025Updated last year
- MoSAIC: Modular system for Acceleration Integration MoSAIC☆10Jul 16, 2026Updated 2 months ago
- Mako is a low-pause, high-throughput garbage collector designed for memory-disaggregated datacenters.☆15Sep 2, 2024Updated 2 years ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆49Jan 16, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 3 years ago
- SYCL materials for ENCCS workshop☆25Apr 25, 2023Updated 3 years ago
- ☆12Oct 19, 2014Updated 11 years ago
- HeteroRefactor: Refactoring for Heterogeneous Computing with FPGA☆11Mar 13, 2026Updated 6 months ago
- ASKAP Benchmark Packages☆13Nov 3, 2023Updated 2 years ago
- Keras implementation of the multi-channel cascaded architecture introduced in the paper "Brain Tumor Segmentation with Deep Neural Networ…☆23Jan 22, 2018Updated 8 years ago
- Preconditioned forward/backward clean algorithm☆12Updated this week