intel / FPGA-DevcloudLinks
Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
☆120Updated 2 years ago
Alternatives and similar repositories for FPGA-Devcloud
Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below
Sorting:
- Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware☆48Updated last year
- ☆118Updated 4 years ago
- Avnet Board Definition Files☆133Updated last week
- ☆295Updated 3 weeks ago
- SystemC/C++ library of commonly-used hardware functions and components for HLS.☆281Updated 4 months ago
- FOS - FPGA Operating System☆71Updated 4 years ago
- A SystemC productivity library: https://minres.github.io/SystemC-Components/☆114Updated this week
- Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy☆383Updated 2 months ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆89Updated 6 months ago
- Brief SystemC getting started tutorial☆93Updated 6 years ago
- Advanced Interface Bus (AIB) die-to-die hardware open source☆140Updated 11 months ago
- PYNQ Composabe Overlays☆73Updated last year
- Virtual Platform for NVDLA☆151Updated 7 years ago
- Verilator open-source SystemVerilog simulator and lint system☆40Updated this week
- Introductory examples for using PYNQ with Alveo☆51Updated 2 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆324Updated 7 months ago
- ☆131Updated 3 months ago
- An overview of TL-Verilog resources and projects☆82Updated 5 months ago
- PYNQ support and examples for Kria SOMs☆112Updated last year
- OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology☆71Updated last year
- PandA-bambu public repository☆282Updated 2 weeks ago
- Tutorials on HLS Design☆52Updated 5 years ago
- This is a Clang tool that parses SystemC models, and synthesizes Verilog from it.☆87Updated 11 months ago
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆111Updated last year
- ☆222Updated last month
- Build Customized FPGA Implementations for Vivado☆338Updated this week
- Board files to build Ultra 96 PYNQ image☆157Updated 8 months ago
- Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs☆104Updated 7 months ago
- Hammer: Highly Agile Masks Made Effortlessly from RTL☆292Updated 4 months ago
- SDAccel Development Environment Tutorials☆110Updated 5 years ago