Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
☆123Jul 17, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA-Devcloud
Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below
Sorting:
- ☆46Sep 30, 2025Updated 5 months ago
- ☆55Jan 26, 2023Updated 3 years ago
- ☆46May 28, 2023Updated 2 years ago
- Shakti: development platform for PlatformIO☆35May 31, 2022Updated 3 years ago
- Intel® FPGA Runtime for OpenCL™ Software Technology☆36Feb 25, 2025Updated last year
- TerosHDL documentation☆13Jul 27, 2025Updated 7 months ago
- ☆35Sep 10, 2024Updated last year
- RISC-V Integrated Matrix Development Repository☆21Mar 13, 2026Updated last week
- ☆30Jan 7, 2023Updated 3 years ago
- Main page☆32Feb 12, 2020Updated 6 years ago
- Quartus Lite docker☆38Sep 26, 2020Updated 5 years ago
- ☆13Jan 27, 2026Updated last month
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- ☆133Updated this week
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 5 years ago
- ☆18Jul 3, 2025Updated 8 months ago
- Student starter code for Fall 2019 labs☆13Nov 28, 2019Updated 6 years ago
- Vitis_Accel_Examples☆585Mar 12, 2026Updated last week
- SystemVerilog Tutorial☆197Mar 7, 2026Updated 2 weeks ago
- SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM☆124Nov 4, 2024Updated last year
- ☆768Jan 22, 2026Updated last month
- Filter builder tool☆18Apr 11, 2022Updated 3 years ago
- ☆27Feb 15, 2025Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- Implementation of a cache memory in verilog☆15Dec 5, 2017Updated 8 years ago
- Samples for Intel® oneAPI Toolkits☆1,128Feb 27, 2026Updated 3 weeks ago
- SYCL Academy, a set of learning materials for SYCL heterogeneous programming☆527Feb 13, 2026Updated last month
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆28Jun 22, 2024Updated last year
- Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.☆13Nov 24, 2017Updated 8 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆336Jan 20, 2025Updated last year
- MoSAIC: Modular system for Acceleration Integration MoSAIC☆10Aug 22, 2025Updated 6 months ago
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆46Jan 16, 2023Updated 3 years ago
- Release KiteRF is a SDR system with K210 & FPGA & ESP32 as its core controller, which make SDR more intelligent, portable and cheap.☆25May 6, 2020Updated 5 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 2 years ago
- SYCL materials for ENCCS workshop☆25Apr 25, 2023Updated 2 years ago
- ASKAP Benchmark Packages☆13Nov 3, 2023Updated 2 years ago
- Preconditioned forward/backward clean algorithm☆12Updated this week