Get started using Intel® FPGA tools on the Devcloud with tutorials, workshops, advanced courses, and sample projects built specifically for students, researchers, and developers. Visit our official Intel® FPGA Devcloud website:
☆123Jul 17, 2023Updated 2 years ago
Alternatives and similar repositories for FPGA-Devcloud
Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆46Apr 1, 2026Updated 3 weeks ago
- ☆55Jan 26, 2023Updated 3 years ago
- ☆46May 28, 2023Updated 2 years ago
- Intel® FPGA Runtime for OpenCL™ Software Technology☆36Feb 25, 2025Updated last year
- ☆14Mar 12, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆35Sep 10, 2024Updated last year
- ☆30Jan 7, 2023Updated 3 years ago
- BLAS implementation for Intel FPGA☆78Nov 18, 2020Updated 5 years ago
- ☆24May 8, 2015Updated 10 years ago
- "mmult" example using SDSoC for PYNQ board☆11Feb 23, 2017Updated 9 years ago
- Simulated Annealing for MAX-CUT problems on {+1,-1}-weighted complete graphs☆13Feb 2, 2019Updated 7 years ago
- https://ve0x10.in/idf-notes-sra/☆13May 27, 2020Updated 5 years ago
- ☆134Updated this week
- ☆18Jul 3, 2025Updated 9 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Student starter code for Fall 2019 labs☆13Nov 28, 2019Updated 6 years ago
- C++ template meta-programmable framework for authoring Pintools☆37Apr 1, 2020Updated 6 years ago
- SYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM☆124Nov 4, 2024Updated last year
- ☆22Aug 31, 2022Updated 3 years ago
- SystemVerilog Tutorial☆207Mar 7, 2026Updated last month
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆93Mar 9, 2026Updated last month
- Open Programmable Acceleration Engine☆269Apr 21, 2026Updated last week
- ☆783Mar 20, 2026Updated last month
- Filter builder tool☆18Apr 11, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆26Feb 15, 2025Updated last year
- Open Source Verification Bundle for VHDL and System Verilog☆48Jan 12, 2024Updated 2 years ago
- oneAPI Specification source files☆213Apr 21, 2026Updated last week
- Log file scanner used with EDA tools to classify errors and warnings☆12Nov 14, 2022Updated 3 years ago
- ☆21Mar 25, 2024Updated 2 years ago
- ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor☆11Aug 23, 2017Updated 8 years ago
- A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.☆338Jan 20, 2025Updated last year
- This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.☆46Jan 16, 2023Updated 3 years ago
- Mako is a low-pause, high-throughput garbage collector designed for memory-disaggregated datacenters.☆15Sep 2, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Release KiteRF is a SDR system with K210 & FPGA & ESP32 as its core controller, which make SDR more intelligent, portable and cheap.☆25May 6, 2020Updated 5 years ago
- A novel spatial accelerator for horizontal diffusion weather stencil computation, as described in ICS 2023 paper by Singh et al. (https:/…☆22Jul 27, 2023Updated 2 years ago
- SYCL materials for ENCCS workshop☆25Apr 25, 2023Updated 3 years ago
- LMAC Core1 - Ethernet 1G/100M/10M☆19Apr 3, 2023Updated 3 years ago
- ASKAP Benchmark Packages☆13Nov 3, 2023Updated 2 years ago
- Preconditioned forward/backward clean algorithm☆12Apr 22, 2026Updated last week
- Keras implementation of the multi-channel cascaded architecture introduced in the paper "Brain Tumor Segmentation with Deep Neural Networ…☆23Jan 22, 2018Updated 8 years ago