Alternatives and similar repositories for FPGA-Devcloud

Users that are interested in FPGA-Devcloud are comparing it to the libraries listed below

• Xilinx / XilinxBoardStore
  ☆299Updated this week
• Xilinx / Vitis-In-Depth-Tutorial
  ☆117Updated 4 years ago
• Xilinx / xup_compute_acceleration
  Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
  ☆48Updated last year
• nvdla / vp
  Virtual Platform for NVDLA
  ☆153Updated 7 years ago
• Xilinx / Alveo-PYNQ
  Introductory examples for using PYNQ with Alveo
  ☆52Updated 2 years ago
• NVlabs / matchlib
  SystemC/C++ library of commonly-used hardware functions and components for HLS.
  ☆282Updated 3 weeks ago
• OpenCAPI / oc-accel
  OpenCAPI Acceleration Framework: develop an accelerator with OpenCAPI technology
  ☆71Updated last year
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆111Updated 2 years ago
• Xilinx / Vivado-Design-Tutorials
  ☆227Updated 2 months ago
• MicrochipTech / fpga-hls-examples
  Open-Source HLS Examples for Microchip FPGAs
  ☆48Updated 2 months ago
• Xilinx / Vitis_Embedded_Platform_Source
  ☆132Updated 3 months ago
• FPGA-Research / fos
  FOS - FPGA Operating System
  ☆72Updated 4 years ago
• Avnet / bdf
  Avnet Board Definition Files
  ☆135Updated 3 weeks ago
• xupgit / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆103Updated 5 years ago
• Xilinx / SDAccel-Tutorials
  SDAccel Development Environment Tutorials
  ☆111Updated 5 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆89Updated 7 months ago
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆284Updated last week
• Minres / SystemC-Components
  A SystemC productivity library: https://minres.github.io/SystemC-Components/
  ☆117Updated last week
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆219Updated last year
• OPAE / intel-fpga-bbb
  Basic Building Blocks (BBB) for OPAE-managed Intel FPGAs
  ☆104Updated 8 months ago
• sld-columbia / esp
  Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
  ☆384Updated 2 months ago
• definelicht / hlslib
  A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
  ☆328Updated 8 months ago
• Xilinx / XilinxCEDStore
  This store contains Configurable Example Designs.
  ☆51Updated last week
• Xilinx / RapidWright
  Build Customized FPGA Implementations for Vivado
  ☆343Updated this week
• Avnet / Ultra96-PYNQ
  Board files to build Ultra 96 PYNQ image
  ☆157Updated 3 weeks ago
• chipsalliance / verilator
  Verilator open-source SystemVerilog simulator and lint system
  ☆41Updated this week
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆40Updated 2 years ago
• intel / fpga-training
  ☆33Updated last year
• Fraunhofer-IMS / airisc_core_complex
  Fraunhofer IMS processor core. RISC-V ISA (RV32IM) with additional peripherals for embedded AI applications and smart sensors.
  ☆96Updated 3 months ago
• Xilinx / Kria-PYNQ
  PYNQ support and examples for Kria SOMs
  ☆115Updated last year