☆19Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for UETRV_ESoC
Users that are interested in UETRV_ESoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Jun 1, 2026Updated last month
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- The best AES cipher built upon tiny-aes-c. Replace tiny-aes-c code blocks with something else if you want to run it on enterprise servers…☆12Mar 29, 2025Updated last year
- Share JTAG chain within RISCV core and Xilinx FPGA.☆10Sep 17, 2019Updated 6 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- Lichee Tang FPGA board examples☆32Dec 15, 2018Updated 7 years ago
- ☆10Feb 3, 2017Updated 9 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- 计算机组成原理课程设计内容，设计一个兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水结构），并增加IO模块（人机交互式），解决数据依赖问题☆13Jun 24, 2020Updated 6 years ago
- LLVM 2.9 branch with TI C64x backend.☆11Oct 17, 2019Updated 6 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆91Mar 17, 2026Updated 4 months ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- ☆16Mar 31, 2023Updated 3 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- A chip8 emulator written in Rust.☆14Dec 12, 2023Updated 2 years ago
- Flutter 高德地图☆16Aug 5, 2021Updated 4 years ago
- Libraries used by multiple RepRapFirmware projects☆10Updated this week
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- ☆12Apr 5, 2021Updated 5 years ago
- ☆13Jan 20, 2021Updated 5 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- Documentation relevant to the available repositories on RISCV-on-Microsemi-FPGA☆14Nov 21, 2018Updated 7 years ago
- Cloud Computing course project. Online Document Collaborative Editing Platform Based on Self-built Distributed File System(write a GFS in…☆18Sep 25, 2021Updated 4 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- FACE: Fast and Customizable Sorting Accelerator☆11Sep 6, 2016Updated 9 years ago
- 64-bit RISC-V processor☆18Nov 30, 2022Updated 3 years ago
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆14Nov 25, 2018Updated 7 years ago
- ☆18Dec 13, 2022Updated 3 years ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆15Jun 26, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- archlinux的loongarch64-bootstrap版本(为了可以迅速迭代跟进上游工具链，archlinux-loongarch64-bootstrap只滚动base-devel包组)，基础工具链源码取自上游开源社区最新状态的linux/gcc/glibc/bin…☆10Jun 8, 2022Updated 4 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 5 years ago
- CKLink_Lite☆12Oct 18, 2021Updated 4 years ago
- Personal Page☆12Jul 4, 2026Updated 3 weeks ago
- ARMv8 hypervisor. Custom Linux KVM variant with the guest and the host memory protection, integrity verification and encryption support.☆27Feb 22, 2024Updated 2 years ago