☆19Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for UETRV_ESoC
Users that are interested in UETRV_ESoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Nov 19, 2025Updated 5 months ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- Lichee Tang FPGA board examples☆32Dec 15, 2018Updated 7 years ago
- ☆17Apr 7, 2022Updated 4 years ago
- Semihosting for AArch64, ARM, RISC-V, LoongArch, MIPS, and Xtensa.☆22Apr 26, 2026Updated last week
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆13Jan 8, 2019Updated 7 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- LLVM 2.9 branch with TI C64x backend.☆11Oct 17, 2019Updated 6 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Open-source RISC-V cryptographic hardware token, RTL repo☆20Nov 9, 2022Updated 3 years ago
- ☆16Mar 31, 2023Updated 3 years ago
- ☆13Jan 20, 2021Updated 5 years ago
- Libraries used by multiple RepRapFirmware projects☆10Apr 28, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Coarse Grained Reconfigurable Arrays with Chisel3☆12Jul 1, 2024Updated last year
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- Documentation relevant to the available repositories on RISCV-on-Microsemi-FPGA☆14Nov 21, 2018Updated 7 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆12Mar 25, 2022Updated 4 years ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- FPGA创新设计大赛全国二等奖，Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆11Aug 16, 2024Updated last year
- A Goldschmidt integer divider written in verilog. Similar to Newton-Raphson but the divison step can be pipelined.☆16Apr 25, 2024Updated 2 years ago
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- R2MDC FFT/IFFT processor adaptive to 64/128/256/512 point☆18Dec 23, 2025Updated 4 months ago
- archlinux的loongarch64-bootstrap版本(为了可以迅速迭代跟进上游工具链，archlinux-loongarch64-bootstrap只滚动base-devel包组)，基础工具链源码取自上游开源社区最新状态的linux/gcc/glibc/bin…☆10Jun 8, 2022Updated 3 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- ☆17Feb 16, 2023Updated 3 years ago
- Bootloader for Texas Instruments C2000 MCU using CANopenNode☆18Apr 14, 2026Updated 3 weeks ago
- Implementation of BitonicSorting algorithm on FPGA through SDAccel using Opencl as source code☆17Nov 21, 2016Updated 9 years ago
- CKLink_Lite☆12Oct 18, 2021Updated 4 years ago
- Nuclei AI Library Optimized For RISC-V Vector☆15Oct 15, 2025Updated 6 months ago
- 64-bit RISC-V processor☆17Nov 30, 2022Updated 3 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Apr 20, 2026Updated 2 weeks ago
- Port of EDK2 implementation of UEFI to RISC-V. See documentation at:☆26Jan 9, 2022Updated 4 years ago
- This c++ implementation RANSAC algorithm finds the n best fitting circles out of the given points.☆15Dec 13, 2016Updated 9 years ago
- ACI-GetStarted☆11Jun 4, 2025Updated 11 months ago
- ☆17Mar 21, 2026Updated last month
- Smart On-Chip Debugger☆24Jun 14, 2023Updated 2 years ago
- SDK for RV32M1 RISCV cores☆17Apr 18, 2019Updated 7 years ago