ee-uet / UETRV_ESoCView external linksLinks
☆19Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for UETRV_ESoC
Users that are interested in UETRV_ESoC are comparing it to the libraries listed below
Sorting:
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆60Nov 19, 2025Updated 2 months ago
- Lichee Tang FPGA board examples☆32Dec 15, 2018Updated 7 years ago
- EBAZ4205 is Xilinx Zynq based mining board used in Ebang Ebit E9+ bitcoin miner machine.☆10Jan 18, 2022Updated 4 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- 2048 Game created via Verilog, loaded on an FPGA board and VGA monitor.☆12Mar 25, 2022Updated 3 years ago
- LLVM 2.9 branch with TI C64x backend.☆11Oct 17, 2019Updated 6 years ago
- PHP Crash Course Source code files☆15Feb 22, 2025Updated 11 months ago
- 计算机组成原理课程设计内容,设计一个兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水结构),并增加IO模块(人机交互式),解决数据依赖问题☆12Jun 24, 2020Updated 5 years ago
- A 32 bit RISC-V SoC (picorv32) on Lattice MXO2 (step fpga)☆10Jan 18, 2021Updated 5 years ago
- gosocks is a golang based implementation of a socks5 server which supports custom handlers☆12Jan 19, 2026Updated 3 weeks ago
- ☆13Dec 2, 2025Updated 2 months ago
- ☆10Feb 27, 2020Updated 5 years ago
- A fault tolerant version of the T03x core, using triple redundancy approach to ensure fault tolrance☆16Aug 24, 2024Updated last year
- Nuclei AI Library Optimized For RISC-V Vector☆14Oct 15, 2025Updated 3 months ago
- SystemVerilog examples for a digital design course☆13Mar 30, 2021Updated 4 years ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- ACI-GetStarted☆11Jun 4, 2025Updated 8 months ago
- IceCreamSwap main features (swap, farm, staking, bridge)☆10Oct 25, 2025Updated 3 months ago
- ☆10Feb 3, 2017Updated 9 years ago
- ☆10May 26, 2023Updated 2 years ago
- https://zig.day☆11Updated this week
- ☆17Apr 7, 2022Updated 3 years ago
- ☆14Jan 23, 2026Updated 3 weeks ago
- Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.☆16May 28, 2021Updated 4 years ago
- KBank Credit Card Statement PDF Parser☆11Mar 3, 2023Updated 2 years ago
- CKLink_Lite☆11Oct 18, 2021Updated 4 years ago
- ☆11Feb 27, 2023Updated 2 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- EVE Online Visual Intel Tool☆11Apr 18, 2018Updated 7 years ago
- Cryptography Library using hardware-accelerated ARM CryptoCell CC310 on nRF52-based Bluefruit☆11Oct 14, 2023Updated 2 years ago
- Unified System Interface, framework, server, GUI and Remote API☆14Nov 20, 2025Updated 2 months ago
- ☆13Nov 9, 2023Updated 2 years ago
- smart router contracts☆11Apr 11, 2025Updated 10 months ago
- Python script for controlling the debug-jtag port of riscv cores☆15Mar 27, 2021Updated 4 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- Orbs staking contract on EVM used for Orbs Proof-of-Stake☆11Jan 24, 2023Updated 3 years ago
- UnixFS commands for helia☆16Jan 8, 2024Updated 2 years ago
- ☆10Aug 23, 2024Updated last year
- Bootloader for Texas Instruments C2000 MCU using CANopenNode☆17Oct 12, 2025Updated 4 months ago