☆19Jan 16, 2024Updated 2 years ago
Alternatives and similar repositories for UETRV_ESoC
Users that are interested in UETRV_ESoC are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Linux Capable 32-bit RISC-V based SoC in System Verilog☆59Jun 1, 2026Updated 4 months ago
- The working draft to split rocket core out from rocket chip☆14Dec 22, 2023Updated 2 years ago
- Share JTAG chain within RISCV core and Xilinx FPGA.☆10Sep 17, 2019Updated 7 years ago
- Lichee Tang FPGA board examples☆32Dec 15, 2018Updated 7 years ago
- ☆10Feb 3, 2017Updated 9 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆12Jan 8, 2022Updated 4 years ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- ☆13Jan 8, 2019Updated 7 years ago
- LLVM 2.9 branch with TI C64x backend.☆11Oct 17, 2019Updated 6 years ago
- Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.☆93Sep 24, 2026Updated 2 weeks ago
- ☆16Mar 31, 2023Updated 3 years ago
- Coarse Grained Reconfigurable Arrays with Chisel3☆11Jul 1, 2024Updated 2 years ago
- Libraries used by multiple RepRapFirmware projects☆10Oct 6, 2026Updated last week
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Nov 6, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆12Apr 5, 2021Updated 5 years ago
- This project was made to more easily "port" the CANopenNode open source library. Contains sample projects made with STM32, ESP32, TI (TMS…☆16Jul 16, 2023Updated 3 years ago
- ☆13Jan 20, 2021Updated 5 years ago
- Bluetooth Low Energy receiver for SDR devices with GNU Radio☆15Oct 10, 2023Updated 3 years ago
- Documentation relevant to the available repositories on RISCV-on-Microsemi-FPGA☆14Nov 21, 2018Updated 7 years ago
- ☆13Nov 9, 2023Updated 2 years ago
- FPGA创新设计大赛全国二等奖,Multi-functional Game Console Based on RISC-V.(基于紫光FPGA的RSIC V多功能游戏机)☆15Aug 16, 2024Updated 2 years ago
- ☆10Feb 27, 2020Updated 6 years ago
- Allwinner V3s Boot ROM Reverse Engineering☆20Feb 18, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- ☆17Feb 16, 2023Updated 3 years ago
- 64-bit RISC-V processor☆18Nov 30, 2022Updated 3 years ago
- Code templates to get started experimenting with the RISC-V LLVM toolchain☆14Nov 25, 2018Updated 7 years ago
- ☆18Dec 13, 2022Updated 3 years ago
- This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, Syst…☆17Jun 26, 2024Updated 2 years ago
- archlinux的loongarch64-bootstrap版本(为了可以迅速迭代跟进上游工具链,archlinux-loongarch64-bootstrap只滚动base-devel包组),基础工具链源码取自上游开源社区最新状态的linux/gcc/glibc/bin…☆10Jun 8, 2022Updated 4 years ago
- Open-Source EDA workshop for RISC-V community☆12Jul 27, 2022Updated 4 years ago
- canopenOnF28335☆15May 27, 2016Updated 10 years ago
- Python script for controlling the debug-jtag port of riscv cores☆16Mar 27, 2021Updated 5 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- CKLink_Lite☆12Oct 18, 2021Updated 4 years ago
- Personal Page☆12Jul 4, 2026Updated 3 months ago
- EVE Online Visual Intel Tool☆11Apr 18, 2018Updated 8 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆90Oct 6, 2022Updated 4 years ago
- This c++ implementation RANSAC algorithm finds the n best fitting circles out of the given points.