dsdnu / zynet
☆21Updated 4 years ago
Alternatives and similar repositories for zynet
Users that are interested in zynet are comparing it to the libraries listed below
Sorting:
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 6 months ago
- FPGA Design of a Neural Network for Color Detection☆75Updated 3 months ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆151Updated 10 months ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆76Updated last year
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆148Updated 4 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆108Updated 5 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- UVM and System Verilog Manuals☆42Updated 6 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆54Updated last year
- Verilog HDL files☆138Updated 11 months ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 8 months ago
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆19Updated last year
- This is a verilog implementation of 4x4 systolic array multiplier☆53Updated 4 years ago
- ☆265Updated last year
- An implementation of the CORDIC algorithm in Verilog.☆94Updated 6 years ago
- A vision transformer based framework for classifying executable images as benign or malicious☆10Updated last year
- A 2D convolution hardware implementation written in Verilog☆45Updated 4 years ago
- This repository contains the design files of RISC-V Single Cycle Core☆43Updated last year
- RISC V core implementation using Verilog.☆26Updated 4 years ago
- ☆52Updated 6 years ago
- ☆55Updated 10 months ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)☆35Updated 3 years ago
- PYNQ support and examples for Kria SOMs☆107Updated 8 months ago
- How to Accelerate an Image Upscaling CNN on FPGA Using HLS☆24Updated 3 years ago
- Implementation of RISC-V RV32I☆18Updated 2 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆84Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆11Updated 10 months ago