Alternatives and similar repositories for zynet

Users that are interested in zynet are comparing it to the libraries listed below

• Marco-Winzker / NN_RGB_FPGA
  FPGA Design of a Neural Network for Color Detection
  ☆76Updated 4 months ago
• Kobzon86 / Convolutional-Neural-Network-using-SystemVerilog
  Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )
  ☆59Updated 7 months ago
• StefanSredojevic / Deep-Neural-Network-Hardware-Accelerator
  SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…
  ☆110Updated 5 years ago
• mehwish411 / 5-Staged-Pipelined-RISC-V-32I-Processor
  5 stage pipeline implementation of RISC-V 32I Processor.
  ☆11Updated 6 months ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆152Updated 11 months ago
• rajdeep66 / edaBundle_whyRD
  opensource EDA tool flor VLSI design
  ☆33Updated last year
• Marco-Winzker / FPGA-Vision
  Learn about image processing with an FPGA. Video lectures explain algorithm and implementation of lane detection for automotive driving. …
  ☆35Updated last year
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆62Updated 3 years ago
• Marco-Winzker / NN_Pattern_FPGA
  Neural Network for Pattern Recognition on an FPGA. Project for Education. Video lectures explain training of the network and FPGA impleme…
  ☆23Updated last year
• ivanvig / 2dconv-FPGA
  A 2D convolution hardware implementation written in Verilog
  ☆47Updated 4 years ago
• AnoushkaTripathi / NASSCOM-VSD-SoC-design-Program
  In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…
  ☆11Updated 9 months ago
• SkillSurf / systemverilog
  SystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
  ☆40Updated last month
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆42Updated last year
• AhmedAalaaa / 32-point-FFT-Verilog-design-based-DIT-butterfly-algorithm
  This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…
  ☆54Updated last year
• padhi499 / Image-Classification-using-CNN-on-FPGA
  Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
  ☆148Updated 4 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆123Updated last year
• Gowtham1729 / Image-Processing
  Image Processing Toolbox in Verilog using Basys3 FPGA
  ☆201Updated 2 weeks ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆22Updated last year
• TheSUPERCD / 8bit_MicroComputer_Verilog
  This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a…
  ☆56Updated 2 years ago
• Marco-Winzker / FPGA-FIR-Filter
  Lecture about FIR filter on an FPGA
  ☆12Updated last year
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆54Updated 4 years ago
• hell03end / verilog-uart
  Simple 8-bit UART realization on Verilog HDL.
  ☆105Updated last year
• EkthaReddy / RISC-V-Single-Cycle-Processor
  In this repository, I have shared the codes for designs and testbenches, Elaborated Design and Simulation Output for each block of RISC-V…
  ☆10Updated 9 months ago
• vinayrayapati / rv32i
  Implementation of RISC-V RV32I
  ☆19Updated 2 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆49Updated 11 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆132Updated 3 years ago
• RClabiisc / I2SRV32-S-v1
  Reconfigurable Computing Lab, DESE, Indian Institiute of Science
  ☆29Updated 2 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆70Updated 5 years ago
• srimanthtenneti / Hell_Fire_SoC_Demo
  ☆24Updated 7 months ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆60Updated 2 years ago