Alternatives and similar repositories for j1:

Users that are interested in j1 are comparing it to the libraries listed below

• jamesbowman / swapforth
  Swapforth is a cross-platform ANS Forth
  ☆288Updated last year
• revaldinho / opc
  One Page CPU Project - CPU, Assembler & Emulator each in a single page of code
  ☆82Updated 9 months ago
• howerj / bit-serial
  A bit-serial CPU written in VHDL, with a simulator written in C.
  ☆124Updated 7 months ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆90Updated last year
• zylin / zpu
  The Zylin ZPU
  ☆243Updated 9 years ago
• wfjm / w11
  PDP-11/70 CPU core and SoC
  ☆122Updated 10 months ago
• RobertBaruch / riscv-reboot
  ☆42Updated 4 years ago
• howerj / forth-cpu
  A Forth CPU and System on a Chip, based on the J1, written in VHDL
  ☆344Updated last year
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• jamieiles / oldland-cpu
  Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
  ☆123Updated 9 years ago
• aw / fiveforths
  32-bit RISC-V Forth for microcontrollers
  ☆77Updated 2 months ago
• cpldcpu / MCPU
  MCPU - A Minimal 8Bit CPU in a 32 Macrocell CPLD
  ☆222Updated last month
• zylin / zpugcc
  ☆51Updated 7 years ago
• Anding / N.I.G.E.-Machine
  A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…
  ☆28Updated 4 months ago
• combinatorylogic / soc
  An experimental System-on-Chip with a custom compiler toolchain.
  ☆60Updated 5 years ago
• grahamedgecombe / icicle
  32-bit RISC-V system on chip for iCE40 FPGAs
  ☆305Updated last year
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆84Updated 5 years ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆210Updated 11 months ago
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆29Updated 2 weeks ago
• ThorKn / J1-forth
  Forth for the J1-CPU
  ☆19Updated 8 years ago
• f4pga / prjtrellis
  Documenting the Lattice ECP5 bit-stream format.
  ☆54Updated last year
• knielsen / ice40_viewer
  ☆59Updated last year
• RobertBaruch / lmarv
  Building a RISC-V processor out of LSI logic
  ☆90Updated 4 years ago
• orangecrab-fpga / orangecrab-examples
  Example projects/code for the OrangeCrab
  ☆106Updated 11 months ago
• cliffordwolf / icotools
  Tools and Examples for IcoBoard
  ☆80Updated 3 years ago
• inforichland / freezing-spice
  A pipelined RISCV implementation in VHDL
  ☆94Updated 6 years ago
• ArcaneNibble / yavhdl
  Yet Another VHDL tool
  ☆31Updated 7 years ago
• theandrew168 / bronzebeard
  Minimal assembler and ecosystem for bare-metal RISC-V development
  ☆49Updated last year
• whitequark / Boneless-CPU
  Resource-efficient 16-bit CPU architecture for FPGA control plane
  ☆96Updated last month
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated last year