Alternatives and similar repositories for MIPS-Processor-VHDL

Users that are interested in MIPS-Processor-VHDL are comparing it to the libraries listed below

• theseus-cores / theseus-cores
  Open source FPGA cores for digital signal processing (push mirror from gitlab.com/theseus-cores/theseus-cores)
  ☆16Updated 4 years ago
• BBN-Q / VHDL-FIR-filters
  Synthesizable FIR filters in VHDL
  ☆14Updated 6 years ago
• dominiksalvet / limen-alpha
  Dual-core 16-bit RISC processor
  ☆11Updated last year
• Daniel-And-Jorge / 6.111-Final-Project
  ☆11Updated 8 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆17Updated 6 years ago
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆20Updated 5 years ago
• boschmitt / wishbone
  VHDL Implementation
  ☆13Updated 11 years ago
• ZipCPU / videozip
  A ZipCPU SoC for the Nexys Video board supporting video functionality
  ☆18Updated 10 months ago
• ultraembedded / minispartan6-audio
  miniSpartan6+ (Spartan6) FPGA based MP3 Player
  ☆27Updated 6 years ago
• mjlyons / vSPI
  Verilog implementation of an SPI slave interface. Intially targetted for Atlys devkit (Xilinx Spartan-6) controlled by TotalPhase Cheetah…
  ☆41Updated 9 months ago
• freecores / spacewire
  SpaceWire
  ☆13Updated 11 years ago
• freecores / tiny_aes
  AES
  ☆14Updated 3 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 7 years ago
• IamVNIE / Hardware-Security
  Hardware Security Labs
  ☆30Updated 8 years ago
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆47Updated 5 years ago
• olgirard / openmsp430
  The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
  ☆65Updated 7 years ago
• RobRoyce / fpga_mouse_controller_basys3
  USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and valid…
  ☆16Updated 3 years ago
• jherkenhoff / Bitmap-VHDL-Package
  A vhdl package for reading and writing bitmap files.
  ☆11Updated 7 years ago
• alexforencich / pin-uart
  FPGA board-level debugging and reverse-engineering tool
  ☆38Updated 2 years ago
• geddy11 / netwiz
  Network protocol libraries for VHDL test benches
  ☆13Updated 5 months ago
• apparentlymart / verilog-vga-simulator
  Verilog VPI VGA Simulator using SDL
  ☆11Updated 10 years ago
• makestuff / altera-pcie
  Simple framework for building PCIe-based solutions for Altera FPGAs
  ☆51Updated 5 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆28Updated last month
• diadatp / mips_cpu
  A implementation of a 32-bit single cycle MIPS processor in Verilog.
  ☆20Updated 4 years ago
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆25Updated 7 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆30Updated 7 years ago
• wkoszek / libxbf
  Xilinx Bitstream Format Library. Easily read .bit files from C programs.
  ☆14Updated 9 years ago
• nockieboy / gpu
  Collaborative project to create an advanced GPU, with additional features to flesh-out the peripherals for a home-made, DIY computer.
  ☆16Updated 2 years ago
• AngeloJacobo / FPGA_SDRAM_Controller
  SDRAM controller optimized to a memory bandwidth of 316MB/s
  ☆28Updated 4 years ago
• CoreyChen922 / sata_2_host_controller
  Sata 2 Host Controller for FPGA implementation
  ☆18Updated 7 years ago