Alternatives and similar repositories for glossary_semiconductor_design_terms_for_beginners

Users that are interested in glossary_semiconductor_design_terms_for_beginners are comparing it to the libraries listed below

• ryuz / BinaryBrain
  Binary Neural Network Framework for FPGA(Differentiable LUT)
  ☆161Updated last month
• ryuz / jelly
  Original FPGA platform
  ☆69Updated this week
• kadomoto / poyo-v
  Open source RISC-V IP core for FPGA/ASIC design
  ☆31Updated last year
• panda5mt / KyogenRV
  The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
  ☆46Updated 4 years ago
• polyphony-dev / polyphony
  Polyphony is Python based High-Level Synthesis compiler.
  ☆107Updated 7 months ago
• nlsynth / karuta
  Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for F…
  ☆107Updated 3 years ago
• msyksphinz-self / swimmer_riscv
  Instruction set simulator for RISC-V
  ☆53Updated 5 years ago
• VLSI-JP / VLSI-JP.github.io
  ☆26Updated last week
• fixstars / xg_mac
  10G Ethernet MAC implementation
  ☆21Updated 5 years ago
• nananapo / veryl-riscv-book
  Let's write RISC-V CPU in Veryl!
  ☆53Updated 3 months ago
• shioyadan / advanced-computer-organization
  ☆168Updated last year
• ciniml / seccamp_riscv_cpu
  セキュリティ・キャンプ 2022-2024 RISC-V CPU自作ゼミ 資料置き場
  ☆37Updated 5 months ago
• chadyuu / riscv-chisel-book
  ☆237Updated 2 years ago
• vaj / riscv-os
  A tiny educational OS for RISC-V
  ☆25Updated 11 months ago
• tokuden / NahiViva
  Vivadoの操作を自動化する
  ☆13Updated 4 years ago
• cpuex2019-yokyo / core
  RISC-V (rv32imf) CPU implemented in System Verilog for cpuex2019 @ UTokyo
  ☆13Updated 5 years ago
• arm-university / Introduction-to-Computer-Architecture-Education-Kit
  Gain an understanding of the fundamental topics and concepts of computer architecture including the application of these with modern Arm …
  ☆283Updated 3 months ago
• sakura-internet / nvme-pcie-to-fabrics-proxy
  (under construction) Experimental circuit design for FPGA based PCIe accelerator board providing emulated NVMe/PCIe device that its read/…
  ☆25Updated 2 years ago
• shibatchii / RISC-V
  RISC-V documentation transrate to Japanese.
  ☆73Updated 3 years ago
• moizumi99 / m99_riscv_emulator
  Simple RISC-V emulator
  ☆16Updated 5 years ago
• ciniml / seccamp_2022_riscv_cpu
  セキュリティキャンプ 2022 Y4 RISC-V CPU自作ゼミ 講義資料
  ☆29Updated last year
• NextMicon / NextMiconIDE
  🛠️ Graphical IDE for NextMicon
  ☆28Updated last year
• kazunori279 / CPU32
  Tiny MIPS for Terasic DE0
  ☆36Updated 11 years ago
• i4kimura / chisel-minicpu
  ☆14Updated 6 years ago
• aquaxis / synverll
  ☆15Updated 9 years ago
• cpu-dev / cpu-dev.github.io
  ☆16Updated 5 years ago
• pezy-computing / pzbcm
  Basic Common Modules
  ☆44Updated 3 weeks ago
• msyksphinz-self / support_ca_llvm_book
  ☆142Updated last year
• synthesijer / synthesijer
  ☆52Updated last year
• onikiri / onikiri2
  ☆39Updated last year