Alternatives and similar repositories for CSF342-Computer-Architecture

Users that are interested in CSF342-Computer-Architecture are comparing it to the libraries listed below

• adithyasunil26 / Y86-64-Processor
  A Y86-64 processor implemented using Verilog
  ☆16Updated 4 years ago
• robertdunne / FPGA-ARM
  Verilog source code for book: Computer Architecture Tutorial
  ☆26Updated 4 years ago
• digital-design-hq / Digital-Resources
  ☆61Updated 3 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆75Updated 2 years ago
• silicon-vlsi / VLSI-2024
  Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.
  ☆11Updated 2 years ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆95Updated 7 months ago
• fcayci / vhdl-digital-design
  VHDL code examples for a digital design course
  ☆21Updated 5 years ago
• vedic-partap / Computer-Organization-and-Architecture-LAB
  Solution to COA LAB Assgn, IIT Kharagpur
  ☆36Updated 6 years ago
• wjoeyzhewei / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆11Updated 6 years ago
• taneroksuz / rv-diios
  6-stage dual-issue in-order superscalar risc-v cpu with floating point unit
  ☆14Updated 3 weeks ago
• supratimdas / NoobsCpu-8bit
  A simple 8bit CPU.
  ☆26Updated 10 months ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆111Updated 2 months ago
• SubZer0811 / VLSI
  All the projects and assignments done as part of VLSI course.
  ☆20Updated 5 years ago
• abdelazeem201 / SoC-Implementation-of-OpenMSP430-Microcontroller
  The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…
  ☆15Updated 3 years ago
• merledu / azadi-soc
  Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.
  ☆32Updated 2 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆27Updated 4 years ago
• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆24Updated 4 years ago
• openhwgroup / cvw-arch-verif
  The purpose of the repo is to support CORE-V Wally architectural verification
  ☆14Updated last week
• siddharth23-8 / 32-bit-RISC-V-Cpu-Core
  ☆35Updated 3 years ago
• fabriziotappero / opencores-scraper
  few python scripts to clone all IP cores from opencores.org
  ☆24Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆120Updated last month
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆61Updated 2 weeks ago
• dominiksalvet / limen-alpha
  Dual-core 16-bit RISC processor
  ☆11Updated last year
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 3 years ago
• sarthak268 / Embedded_Logic_and_Design
  This repository contains all labs done as a part of the Embedded Logic and Design course.
  ☆25Updated 7 years ago
• dominiksalvet / risc63
  Custom 64-bit pipelined RISC processor
  ☆18Updated last year
• RobRoyce / fpga_mouse_controller_basys3
  USB-to-PS2 mouse controller for FPGAs written in Verilog. Performs clock division, signal sampling, processing, error checking, and valid…
  ☆16Updated 3 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated last year
• shrut1996 / Cache-Implementation
  Implementation of a cache memory in verilog
  ☆14Updated 7 years ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆28Updated last month