abbas-rahimi / HDC-Language-Recognition
Hyperdimensional computing for language recognition: Matlab and RTL implementations
☆30Updated 7 years ago
Related projects: ⓘ
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆54Updated last year
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆71Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆50Updated 5 months ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆50Updated 3 years ago
- ☆39Updated 7 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆44Updated 3 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆19Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆104Updated 7 months ago
- Fully opensource spiking neural network accelerator☆119Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆30Updated 4 years ago
- Stochastic Computing for Deep Neural Networks☆28Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆40Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆58Updated last month
- Library of approximate arithmetic circuits☆46Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆63Updated 9 months ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆28Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.☆31Updated 6 months ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆8Updated 3 years ago
- ☆81Updated 3 months ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆133Updated 10 months ago
- IC implementation of TPU☆84Updated 4 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆34Updated last year
- ☆14Updated 5 months ago
- ☆16Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago
- A Simulation Framework for Memristive Deep Learning Systems☆134Updated 4 months ago
- Compact LSTM inference kernel (CLINK) designed in C/HLS for FPGA implementation.☆17Updated 4 years ago
- Architecture for RRAM multilevel programming☆16Updated 6 years ago
- Models and examples built with hls4ml☆12Updated 4 years ago