abbas-rahimi / HDC-Language-RecognitionLinks
Hyperdimensional computing for language recognition: Matlab and RTL implementations
☆37Updated 8 years ago
Alternatives and similar repositories for HDC-Language-Recognition
Users that are interested in HDC-Language-Recognition are comparing it to the libraries listed below
Sorting:
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆53Updated 4 years ago
- Central repository for all NeuroSim versions. Each version is uploaded in a separate branch. Updates to the versions will be reflected he…☆73Updated last month
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆87Updated 3 years ago
- ☆13Updated 7 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- ☆48Updated last year
- Verilog and Python drivers and APIs for Neurram 48-core chip☆41Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆62Updated 4 years ago
- Benchmark framework of 3D integrated CIM accelerators for popular DNN inference, support both monolithic and heterogeneous 3D integration☆24Updated 4 years ago
- Stochastic Computing for Deep Neural Networks☆33Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆16Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆167Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆44Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆75Updated 7 months ago
- This repository includes the Resistive Random Access Memory (RRAM) Compiler which is designed in the context of the research project of D…☆70Updated 3 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 6 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆10Updated 4 years ago
- ☆19Updated 2 years ago
- Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.☆24Updated 2 years ago
- ☆34Updated 8 months ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆68Updated 2 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆35Updated 3 years ago
- Architecture for RRAM multilevel programming☆17Updated 7 years ago
- Train and deploy LUT-based neural networks on FPGAs☆98Updated last year
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆43Updated 3 weeks ago
- Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.☆58Updated last year
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆38Updated 6 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆19Updated 5 years ago
- Fully opensource spiking neural network accelerator☆158Updated 2 years ago
- ☆19Updated 4 years ago