WangXuan95 / TinyLZMA
A minimal LZMA data compressor & decompressor in only hundreds of lines of C. 一个只有几百行C代码的LZMA通用数据压缩器和解压器。
☆42Updated last month
Related projects ⓘ
Alternatives and complementary repositories for TinyLZMA
- USB -> AXI Debug Bridge☆35Updated 3 years ago
- A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.☆27Updated 4 years ago
- ☆19Updated 3 years ago
- Another tiny RISC-V implementation☆52Updated 3 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- Ethernet MAC 10/100 Mbps☆24Updated 3 years ago
- GDB Server for interacting with RISC-V models, boards and FPGAs☆20Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆28Updated last month
- An FPGA-based QOI image compressor and decompressor in Verilog. 基于FPGA的QOI图像压缩器和解压器。☆20Updated 2 months ago
- Dual RISC-V DISC with integrated eFPGA☆15Updated 3 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated last year
- SPI通信实现FLASH读写☆13Updated 4 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆32Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- TangMega-138K-example project☆30Updated 2 weeks ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆22Updated 6 years ago
- USB2.0 Verilog☆15Updated 5 years ago
- IEEE 754 single precision floating point library in systemverilog and vhdl☆26Updated last month
- A gdbstub for connecting GDB to a RISC-V Debug Module☆24Updated last month
- A blinky project for the ULX3S v3.0.3 FPGA board☆16Updated 5 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆27Updated 3 years ago
- A simple implementation of the Karatsuba multiplication algorithm☆9Updated 10 months ago
- USB capture IP☆19Updated 4 years ago
- DDR4 Simulation Project in System Verilog☆32Updated 10 years ago
- AXI-4 RAM Tester Component☆16Updated 4 years ago
- turbo 8051☆28Updated 7 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆15Updated last year
- How to use the Intel JTAG primitive without using virtual JTAG☆16Updated 3 years ago
- A simple, scalable, source-synchronous, all-digital DDR link☆19Updated 3 weeks ago