Alternatives and similar repositories for digital-datasheets

Users that are interested in digital-datasheets are comparing it to the libraries listed below

• VHDL / pyVHDLModel
  An abstract language model of VHDL written in Python.
  ☆52Updated this week
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆137Updated last month
• agoessling / rules_vivado
  Bazel rules for Xilinx Vivado
  ☆19Updated 2 years ago
• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆131Updated 3 weeks ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆68Updated this week
• stineje / sky130RHBDlib
  Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130
  ☆6Updated 2 weeks ago
• mattvenn / flipflop_demo
  Flip flop setup, hold & metastability explorer tool
  ☆34Updated 2 years ago
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆238Updated 7 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆90Updated 7 months ago
• Isotel / mixedsim
  Hardware Design Tool - Mixed Signal Simulation with Verilog
  ☆78Updated 5 months ago
• enjoy-digital / litescope
  Small footprint and configurable embedded FPGA logic analyzer
  ☆179Updated last week
• efabless / clear
  ☆69Updated 9 months ago
• olofk / corescore
  CoreScore
  ☆155Updated 4 months ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆132Updated 11 months ago
• pieter3d / simview
  ☆79Updated last year
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆53Updated last month
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆51Updated last year
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆139Updated last week
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆60Updated this week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆48Updated this week
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆179Updated this week
• eskiyerli / revedaRelease
  This repository is for (pre-)release versions of the Revolution EDA.
  ☆42Updated last week
• wallento / wavedrompy
  WaveDrom compatible python command line
  ☆103Updated 2 years ago
• mineda-support / ICPS2023_5
  ☆52Updated 3 months ago
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆57Updated 7 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• phanrahan / mantle
  mantle library
  ☆44Updated 2 years ago
• Paebbels / pyVHDLParser
  Streaming based VHDL parser.
  ☆84Updated 10 months ago
• mattvenn / gtkwave-python-filter-process
  ☆34Updated 4 years ago