edatasheets / digital-datasheets
☆12Updated 2 months ago
Alternatives and similar repositories for digital-datasheets:
Users that are interested in digital-datasheets are comparing it to the libraries listed below
- Bazel rules for Xilinx Vivado☆18Updated 2 years ago
- Building and deploying container images for open source electronic design automation (EDA)☆112Updated 5 months ago
- Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…☆128Updated this week
- Hardware Design Tool - Mixed Signal Simulation with Verilog☆76Updated 3 months ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆133Updated 3 months ago
- Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130☆4Updated 4 months ago
- Experimental flows using nextpnr for Xilinx devices☆229Updated 5 months ago
- Verilog package manager written in Rust☆143Updated 5 months ago
- ☆77Updated last year
- ☆14Updated 6 months ago
- System on Chip toolkit for Amaranth HDL☆86Updated 5 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe☆95Updated last year
- Open-source repository for a standard-cell library characterizer using complete open-source tools☆26Updated 3 weeks ago
- A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.☆43Updated 3 months ago
- Python-based IP-XACT parser☆130Updated 9 months ago
- ☆17Updated this week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆47Updated this week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated last month
- Python script to transform a VCD file to wavedrom format☆75Updated 2 years ago
- Robot Framework KiCad Library☆10Updated 2 years ago
- Small footprint and configurable SPI core☆41Updated 2 months ago
- FuseSoC standard core library☆129Updated 2 months ago
- Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.☆75Updated 3 years ago
- Create fast and efficient standard cell based adders, multipliers and multiply-adders.☆111Updated last year
- Standard and Curated cores, tested and working.☆11Updated 2 years ago
- RISC-V bazel toolchains for GCC compilation☆11Updated 11 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆100Updated last week
- An abstract language model of VHDL written in Python.☆51Updated last week
- Flip flop setup, hold & metastability explorer tool☆34Updated 2 years ago
- Generate address space documentation HTML from compiled SystemRDL input☆50Updated 6 months ago