This project is primarily aimed at showcasing an EDA toolchain based on the OpenClaw framework, in which our own research work is also demonstrated. The project will be continuously updated to support the integration of more of our research outcomes, open-source tools, and commercial tools into the toolchain in the form of additional plugins.
☆66Apr 2, 2026Updated 6 months ago
Alternatives and similar repositories for RTL-CLAW
Users that are interested in RTL-CLAW are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆34May 4, 2025Updated last year
- ☆25May 8, 2025Updated last year
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆32Aug 14, 2026Updated 2 months ago
- Multi-agent inference framework for RTL generation. A Verilog agent and a Python reference-model agent independently propose implementati…☆34Jul 27, 2026Updated 2 months ago
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆55Oct 5, 2026Updated 2 weeks ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆35Jun 5, 2024Updated 2 years ago
- ☆16May 6, 2026Updated 5 months ago
- ☆58Jan 6, 2026Updated 9 months ago
- Gate-level timing estimation toolkit☆25Apr 11, 2022Updated 4 years ago
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆18Oct 15, 2026Updated last week
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆113Jul 29, 2025Updated last year
- Open-source compiler that hardwires ternary BitNet weights into mask-programmed compute-in-ROM silicon on open PDKs☆47Sep 18, 2026Updated last month
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆14Mar 30, 2026Updated 6 months ago
- ☆27Sep 18, 2026Updated last month
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- A SystemVerilog Assertion dataset to improve hardware verification with LLMs.☆30Jun 9, 2025Updated last year
- ☆15Sep 13, 2024Updated 2 years ago
- ☆25Mar 19, 2026Updated 7 months ago
- ☆20Feb 25, 2026Updated 7 months ago
- Fix syntax errors of LLM-generated RTL☆57May 23, 2024Updated 2 years ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆44Jul 9, 2025Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [NeurIPS 2023] CircuitFormer: Circuit as Set of Points☆38Nov 22, 2023Updated 2 years ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆38Mar 12, 2026Updated 7 months ago
- ☆25Apr 9, 2025Updated last year
- ☆15Jun 24, 2025Updated last year
- Xplace 3.0: An Extremely Fast, Extensible and Deterministic Placement Framework with Detailed-Routability and Timing Optimization☆172Jul 8, 2026Updated 3 months ago
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆17Apr 7, 2023Updated 3 years ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆142Apr 11, 2025Updated last year
- Hot & Spicy tool suite☆23Jan 4, 2022Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Generative Benchmark for LLM-Aided Hardware Design☆30Jun 4, 2025Updated last year
- ☆50May 18, 2024Updated 2 years ago
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- GPU-based logic synthesis tool☆111Mar 31, 2026Updated 6 months ago
- Pytorch implementation of the paper "Comprehensive Compact Phenomenological Modeling of Integrated Metal-Oxide Memristors" (https://ieeex…☆11Oct 22, 2023Updated 3 years ago
- Minimal RISC-V Chisel design strictly reflecting the ISA document for verification.☆21Oct 10, 2026Updated last week
- ☆31Dec 8, 2025Updated 10 months ago