This project is primarily aimed at showcasing an EDA toolchain based on the OpenClaw framework, in which our own research work is also demonstrated. The project will be continuously updated to support the integration of more of our research outcomes, open-source tools, and commercial tools into the toolchain in the form of additional plugins.
☆66Apr 2, 2026Updated 6 months ago
Alternatives and similar repositories for RTL-CLAW
Users that are interested in RTL-CLAW are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- [IJCAI 2024] QiMeng-CPU-v1: Automated CPU Design by Learning from Input-Output Examples☆35May 4, 2025Updated last year
- ☆25May 8, 2025Updated last year
- Open Source Cell Library for Predictive CNFET Technology☆16Mar 12, 2026Updated 6 months ago
- EasierUVM from Doulos now written in Python for easier UVM with framework and template generator☆14Sep 28, 2022Updated 4 years ago
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆35Jun 5, 2024Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- VeriFlow-CC: A Claude Code-driven RTL design pipeline. Automates Chip-on-Chat from architecture to synthesis (iVerilog/Yosys) using a sta…☆51Aug 3, 2026Updated 2 months ago
- ☆16May 6, 2026Updated 4 months ago
- ☆58Jan 6, 2026Updated 8 months ago
- (WIP) Open-source Rust gate-level EDA infrastructure: parsers and databases☆22May 2, 2026Updated 5 months ago
- Agent skill for AMD/Xilinx Vitis HLS generation and FPGA design workflows.☆30Aug 14, 2026Updated last month
- Misc documentation and specifications☆14Feb 26, 2022Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆18Feb 22, 2026Updated 7 months ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Dec 14, 2019Updated 6 years ago
- Modular, opensource, high performance G-code interpreter and CNC controller written in Object-Oriented C++☆10Jun 17, 2016Updated 10 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- ☆20Feb 25, 2026Updated 7 months ago
- ☆25Mar 19, 2026Updated 6 months ago
- Fix syntax errors of LLM-generated RTL☆57May 23, 2024Updated 2 years ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 9 months ago
- MCP server to read waveform files☆48Aug 1, 2026Updated 2 months ago
- [NeurIPS 2023] CircuitFormer: Circuit as Set of Points☆38Nov 22, 2023Updated 2 years ago
- ☆25Apr 9, 2025Updated last year
- ☆15Jun 24, 2025Updated last year
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆325Feb 9, 2025Updated last year
- Open source password manager - Proton Pass • AdSecurely store, share, and autofill your credentials with Proton Pass, the end-to-end encrypted password manager trusted by millions.
- GPU-based logic synthesis tool☆111Mar 31, 2026Updated 6 months ago
- This is the Github Repo for the paper: MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis O…☆112Jul 29, 2025Updated last year
- ☆31Dec 8, 2025Updated 9 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆140Apr 11, 2025Updated last year
- UnityChip Verification AI-Agent☆229Updated this week
- Layout Symmetry Annotation for Analog Circuits with GraphNeural Networks☆17Apr 7, 2023Updated 3 years ago
- Generative Benchmark for LLM-Aided Hardware Design☆30Jun 4, 2025Updated last year
- A tool for analysing the source-level static connectivity of a SystemVerilog design☆29Updated this week
- ☆50May 18, 2024Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Hot & Spicy tool suite☆23Jan 4, 2022Updated 4 years ago
- The PULP RI5CY core modified for Verilator modeling and as a GDB server.☆28Jan 11, 2019Updated 7 years ago
- ☆64Mar 10, 2025Updated last year
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- FIR band-pass filter using Verilog HDL.☆14Sep 7, 2026Updated 3 weeks ago
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆61May 21, 2025Updated last year
- FPL'26 Optimization Contest☆54Sep 15, 2026Updated 2 weeks ago