Alternatives and similar repositories for riscv-sim

Users that are interested in riscv-sim are comparing it to the libraries listed below

• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆101Updated 7 months ago
• splinedrive / lets_build_a_compiler_for_riscv
  A c/RISCV of "Let's Build a Compiler" by Jack Crenshaw
  ☆117Updated 3 years ago
• ipacman / xv6-riscv
  Xv6 ports for RISC-V
  ☆14Updated last year
• Mazin-O3 / Veecom
  Simple Yet Powerful RISC-V Computer
  ☆121Updated 11 months ago
• FPGAwars / FLIX-V
  FLIX-V: FPGA, Linux and RISC-V
  ☆41Updated 2 years ago
• sylefeb / tinygpus
  TinyGPUs, making graphics hardware for 1990s games
  ☆164Updated 2 months ago
• x653 / xv6-riscv-fpga
  Build a RISC-V computer system on fpga iCE40HX8K-EVB and run UNIX xv6 using only FOSS (free and open source hard- and software).
  ☆56Updated 2 years ago
• OpenPOWERFoundation / a2i
  The A2I core was used as the general purpose processor for BlueGene/Q, the successor to BlueGene/L and BlueGene/P supercomputers
  ☆47Updated 3 years ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆59Updated 7 months ago
• lcq2 / risc-666
  RISC-V user-mode emulator that runs DooM
  ☆58Updated 6 years ago
• DoctorWkt / ULX3S-Blinky
  A blinky project for the ULX3S v3.0.3 FPGA board
  ☆17Updated 6 years ago
• popovicu / linux-no-mmu-userspace-example
  ☆44Updated 2 years ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆177Updated last month
• franzflasch / riscv_em
  Simple risc-v emulator, able to run linux, written in C.
  ☆144Updated last year
• toddmaustin / bringup-bench
  Bringup-Bench is a collection of standalone minimal library and system dependence benchmarks useful for bringing up newly designed CPUs, …
  ☆218Updated last month
• BrunoLevy / TinyPrograms
  Tiny programs from various sources, for testing softcores
  ☆136Updated 4 months ago
• popovicu / risc-v-bare-metal-fake-bios
  Code for the "fake BIOS" RISC-V example
  ☆35Updated 2 years ago
• FelipeFFerreira / ITA-CORES
  RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32
  ☆54Updated 2 years ago
• stnolting / riscv-gcc-prebuilt
  📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
  ☆107Updated 9 months ago
• stnolting / neorv32-riscof
  ✔️ Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
  ☆37Updated this week
• ZipCPU / eth10g
  10Gb Ethernet Switch
  ☆244Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆162Updated 3 years ago
• zeeshanrafique23 / RV32I-Logisim
  RV32I single cycle simulation on open-source software Logisim.
  ☆21Updated 3 years ago
• JulianKemmerer / PipelineC-Graphics
  Graphics demos
  ☆112Updated last year
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆106Updated 4 years ago
• riadhbenabdelhamid / BRISKI
  BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput …
  ☆28Updated 3 weeks ago
• fmash16 / riscv_emulator
  A basic working RISCV emulator written in C
  ☆74Updated last year
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆139Updated 2 years ago
• OpenPOWERFoundation / a2o
  The A2O core was a follow-on to A2I, written in Verilog, and supported a lower thread count than A2I, but higher performance per thread, …
  ☆51Updated 7 months ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆76Updated last month