Design Space Exploration
☆12Oct 21, 2024Updated last year
Alternatives and similar repositories for opendse
Users that are interested in opendse are comparing it to the libraries listed below
Sorting:
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- A very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric☆14Dec 4, 2018Updated 7 years ago
- Piecewise curve approximation☆10Feb 3, 2016Updated 10 years ago
- An example Hardware Processing Engine☆12Feb 4, 2023Updated 3 years ago
- ☆13Mar 27, 2019Updated 6 years ago
- Manycore platform Simulation tool for NoC-based platform at a Cycle-accurate level☆11Feb 22, 2018Updated 8 years ago
- AxLS: An Open-Source Framework for Netlist Transformation Approximate Logic Synthesis☆13Sep 14, 2025Updated 5 months ago
- tuya_smesh_sdk_tlsr825x_common☆14Nov 24, 2020Updated 5 years ago
- Convert hand-drawn circuit to computer understandable circuit using Machine Learning☆10Feb 3, 2018Updated 8 years ago
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆13Nov 9, 2015Updated 10 years ago
- TopK Algorithms Benchmark☆10Jul 16, 2019Updated 6 years ago
- UVM Clock and Reset Agent☆14Jun 29, 2017Updated 8 years ago
- ☆16Oct 28, 2025Updated 4 months ago
- ☆16Jan 9, 2025Updated last year
- ☆12Oct 25, 2021Updated 4 years ago
- ☆17Oct 7, 2025Updated 4 months ago
- ABACUS is a tool for approximate logic synthesis☆14Jul 13, 2020Updated 5 years ago
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 6 months ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Aug 18, 2017Updated 8 years ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 4 years ago
- ☆13Apr 12, 2022Updated 3 years ago
- QCPINN: Quantum-Classical Physics-Informed Neural Networks☆26Dec 15, 2025Updated 2 months ago
- Microwave doppler effect motion sensor☆19Feb 6, 2022Updated 4 years ago
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Jan 9, 2026Updated last month
- SystemVerilog Constraint Layering via Reusable Randomization Policy Classes Examples☆17Mar 8, 2015Updated 10 years ago
- A Very Simple Vector Database☆15May 1, 2023Updated 2 years ago
- ☆16Oct 30, 2022Updated 3 years ago
- A vector processor implemented in Chisel☆21Aug 3, 2014Updated 11 years ago
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 6 years ago
- ☆10Jul 21, 2011Updated 14 years ago
- Personal functions for making Pyplot Python figures☆20Feb 25, 2026Updated last week
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆17May 30, 2016Updated 9 years ago
- Development and simulation framework for Application Specific Vector Processor☆16Mar 8, 2020Updated 5 years ago
- SystemVerilog language server client for Visual Studio Code☆23Dec 30, 2022Updated 3 years ago
- Ternary Weights and Activations☆25Jul 23, 2018Updated 7 years ago
- Rigorous Floating-Point Mixed-Precision Tuner☆17May 21, 2020Updated 5 years ago
- 机器学习研究☆19Mar 8, 2020Updated 5 years ago
- A Python framework for the batch processing and deconvolution of Raman spectra of carbonaceous materials.☆29Sep 4, 2025Updated 6 months ago
- 用于海底底层结构探测及舰船监测的水听器φ-OTDR仪表开发的上位机软件,能实现UDP通信、文件存储、实时解调、波形显示等功能☆26Mar 19, 2023Updated 2 years ago