OmarBazaraa / Logic-SimulatorLinks
A combinational logic circuit design and simulation app for Windows written in C++ using CMU graphics library.
☆29Updated 7 years ago
Alternatives and similar repositories for Logic-Simulator
Users that are interested in Logic-Simulator are comparing it to the libraries listed below
Sorting:
- Digital/Analog Circuit Design and Simulation System for Windows☆28Updated 6 years ago
- A simple 16-bit CPU built in Logisim☆57Updated 6 years ago
- Graphical user interface for circuit simulation on GNU/Linux using ngspice☆17Updated 9 years ago
- A digital logic simulator inspired by Logisim.☆50Updated 4 years ago
- Gate-Level Simulation on a GPU☆10Updated 9 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 5 years ago
- RISC-V assembler/simulator with GUI☆14Updated 3 years ago
- Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.☆14Updated 7 years ago
- A C++ programming library (based on Qt) for graphical block modeling, with graphical connection editing and serialization of the block sc…☆37Updated 3 years ago
- This is a higan/Verilator co-simulation example/framework☆51Updated 7 years ago
- RISC-V(RV32IM) emulator with support for syscalls.☆30Updated 2 years ago
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆21Updated 3 years ago
- Synthesiser for Asynchronous Verilog Language☆20Updated 11 years ago
- Initialize / Fill C++ array fast - O(1) time with only 1 extra bit of memory.☆31Updated 2 years ago
- A simple UEFI bootloader written in C++17 that does not need any third-party support code like Tianocore EDK or gnu-efi; only needs a han…☆21Updated 3 years ago
- parser combinator and AST generator in c++17☆24Updated 2 years ago
- C11 parser with GNU C extensions written in C++14☆18Updated 7 years ago
- a simple operating system☆10Updated 10 years ago
- A small and simple static analysis tool for C in C☆33Updated last year
- Standalone C compiler for RISC-V and ARM☆95Updated last year
- C-- Compiler using Antlr4☆17Updated 7 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆19Updated 2 years ago
- LALR(1) parser for C++☆80Updated last year
- A Small RISC-V Virtual Machine☆92Updated 3 years ago
- ☆17Updated 2 years ago
- A bit-serial CPU☆19Updated 6 years ago
- C++17 implementation of an AST for Verilog code generation☆24Updated 2 years ago
- FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.☆63Updated last year
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆13Updated 5 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated 2 years ago