OmarBazaraa / Logic-Simulator
A combinational logic circuit design and simulation app for Windows written in C++ using CMU graphics library.
☆24Updated 6 years ago
Related projects: ⓘ
- A LTSPICE like circuit simulation software, base on Qt☆23Updated 4 years ago
- Digital/Analog Circuit Design and Simulation System for Windows☆24Updated 5 years ago
- System on Chip SPARC V8 using leon3 CPU by Gaisler. C++, vhdl, v files.☆11Updated 11 years ago
- Custom 64-bit pipelined RISC processor☆13Updated 2 months ago
- ☆10Updated 6 years ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 2 years ago
- Unix-like operating system for CNC / Machine Control applications☆10Updated 6 years ago
- Simple schematic/diagram editor☆17Updated last year
- Gate-Level Simulation on a GPU☆9Updated 7 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆12Updated 4 years ago
- RISC-V RV32I CPU written in verilog☆10Updated 4 years ago
- ☆12Updated this week
- ☆15Updated 6 years ago
- tools used by project repos to test configuration, generate OpenLane run summaries and documentation☆14Updated last week
- Lightweight C++ Signals and Slots implementation☆23Updated 3 months ago
- Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…☆14Updated 3 years ago
- ☆14Updated 11 months ago
- This is a stand-alone Verilog IDE derived from a QtCreator 3.6.1 subset featuring the VerilogCreator plugin☆17Updated 2 years ago
- Processing Unit with RISCV-32 / RISCV-64 / RISCV-128☆19Updated this week
- Main Repo for the OpenHW Group Software Task Group☆15Updated last week
- RISC-V assembler/simulator with GUI☆12Updated 2 years ago
- C11 parser with GNU C extensions written in C++14☆17Updated 6 years ago
- Intel 8051 microcontroller emulator☆13Updated 2 years ago
- A simple program to convert gdsII files to vector output formats. Currently used to create laser-cut models of standard cells.☆12Updated last year
- Instructions to import Ubuntu guest Virtual Machine for RISC-V development for the VEGA board☆14Updated last year
- Synthesiser for Asynchronous Verilog Language☆19Updated 9 years ago
- Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout☆10Updated 10 years ago
- Mirror of git://git.zerfleddert.de/usb-driver☆17Updated 11 years ago
- Hard Real-Time world-wide clock synchronization utilizing new better algorithms than PTP and NTP uses.☆13Updated 8 years ago
- Open Source Detailed Placement engine☆11Updated 4 years ago