The project includes codes, specification, presentation and other information.
☆27Feb 2, 2026Updated last month
Alternatives and similar repositories for Intelligent-BLDC-driver
Users that are interested in Intelligent-BLDC-driver are comparing it to the libraries listed below
Sorting:
- Step by step tutorial for building CortexM0 SoC☆39Mar 29, 2022Updated 3 years ago
- 【2022集创赛】Arm杯一等奖作品：Cortex-M0智能娱乐收音机 开源项目☆27Mar 21, 2023Updated 3 years ago
- This is just for Takk_Zynq_Labs test.☆27Jan 14, 2022Updated 4 years ago
- Windows Research Kernel☆14Apr 1, 2016Updated 9 years ago
- A custom coprocessor and SoC for hardware security experiments in electronics.☆12May 20, 2017Updated 8 years ago
- ☆14Aug 23, 2023Updated 2 years ago
- FIR，FFT based on Verilog☆14Dec 3, 2017Updated 8 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧，控制DA输出相应正弦信号☆10Jul 10, 2019Updated 6 years ago
- 基于Verilog实现的串口发送程序，带奇偶校验位。☆12Aug 23, 2019Updated 6 years ago
- 使用C语言结合单片机一步一步实现FOC算法控制BLDC电机 Implementing FOC algorithm step by step to control BLDC motor using C language combined with microcontroll…☆26Feb 20, 2024Updated 2 years ago
- 第四届全国大学生嵌入式比赛SoC☆11Apr 1, 2022Updated 3 years ago
- 2023年全国大学生集成电路创新创业大赛-海运捷讯杯-全国二等奖作品 FPGA-Based SSD-MobileNet Acceleator; CNN Acceleator; China IC Competition☆20Dec 2, 2024Updated last year
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆12Jan 15, 2022Updated 4 years ago
- 磁场矢量控制云台电机程序，使用MT6813获取位置角度，使用uart串口实现modbus RTU通讯，电流环16K，速度环8K，位置环4K，STM32F103C8T6主控，开发环境keil☆11Sep 10, 2024Updated last year
- Documentation for the entire CGRAFlow☆19Sep 17, 2021Updated 4 years ago
- 在stm32f407上实现使用以太网进行OTA升级☆20Jul 5, 2025Updated 8 months ago
- Ubuntu 10.04 kernel 2.6.32-kdev☆16Apr 24, 2025Updated 10 months ago
- 第八届集创赛紫光同创杯音频处理国家二等奖☆25Oct 15, 2024Updated last year
- 基于FPGA的PCIe 板卡，支持 离散量输入输出、ARINC429协议☆17Dec 1, 2022Updated 3 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 8 years ago
- 2023 年电赛A题sogi鉴相加pll锁相dq解耦电流环控制☆15Sep 8, 2023Updated 2 years ago
- A 66-order (67 taps) hamming FIR LPF Filter is to be designed with a cutoff frequency of 200 KHZ for a sampling frequency of 1 MHZ☆14Feb 17, 2023Updated 3 years ago
- The 3rd Iteration of the Berkeley RISC-V DMA Accelerator☆28Nov 21, 2019Updated 6 years ago
- An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.☆14Jan 6, 2019Updated 7 years ago
- ☆16Aug 24, 2023Updated 2 years ago
- Verilog UART FIFO that will just echo back characters. Useful for testing the communications path.☆13May 5, 2015Updated 10 years ago
- ☆38Jun 3, 2024Updated last year
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆20May 4, 2017Updated 8 years ago
- I2C Slave☆14Jul 17, 2014Updated 11 years ago
- 为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。☆24Oct 9, 2020Updated 5 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。☆207Sep 15, 2023Updated 2 years ago
- 四轴飞行器飞控算法☆23Aug 26, 2019Updated 6 years ago
- 电池管理系统☆16Jan 13, 2020Updated 6 years ago
- MIDI电子乐器，ESP32、MicroPython☆10Jun 27, 2021Updated 4 years ago
- ☆10Mar 10, 2023Updated 3 years ago
- 文档编写☆13Sep 19, 2020Updated 5 years ago
- CPU + xv6 + compiler☆18Feb 7, 2018Updated 8 years ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Aug 16, 2022Updated 3 years ago