Course project of Computer Architecture, designed by single-cycle datapath. The verilog code could be completely compiled by Quartus II.
☆30Feb 14, 2021Updated 5 years ago
Alternatives and similar repositories for single-cycle-MIPS-CPU
Users that are interested in single-cycle-MIPS-CPU are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Aug 8, 2017Updated 8 years ago
- A implementation of a 32-bit single cycle MIPS processor in Verilog.☆22Nov 23, 2020Updated 5 years ago
- Single-cycle MIPS processor in Verilog HDL.☆10May 1, 2020Updated 6 years ago
- Processor repo☆58Dec 19, 2013Updated 12 years ago
- An implementation of MIPS single cycle datapath in Verilog.☆17Mar 11, 2012Updated 14 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design of a 16-Bit CPU using Verilog☆50Jun 11, 2019Updated 6 years ago
- 5-stage pipelined 32-bit MIPS microprocessor in Verilog☆142Apr 3, 2020Updated 6 years ago
- yolov8pose 部署版本，将DFL放在后处理中，部署rk3588.☆11Aug 21, 2024Updated last year
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- ☆12Sep 2, 2025Updated 8 months ago
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆15Jan 4, 2019Updated 7 years ago
- A blinky project for the ULX3S v3.0.3 FPGA board☆17Jan 16, 2026Updated 4 months ago
- EmonTxV3 Continuous Monitoring Firmware (Default shipped EmonTxV3 firmware)☆13Feb 16, 2023Updated 3 years ago
- A 32-bit MIPS processor used Altera Quartus II with Verilog.☆28Sep 20, 2018Updated 7 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- A classification of whether or not to wear a mask.☆12Oct 12, 2020Updated 5 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) at UMJI.☆11Dec 28, 2020Updated 5 years ago
- Vehicle templates with multibody suspension and electric powertrain sized for Formula Student competitions.☆23Apr 17, 2026Updated last month
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 7 years ago
- ☆12Mar 6, 2019Updated 7 years ago
- Modern CV template for Typst☆12Apr 13, 2026Updated last month
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- This repository contains a detailed description of how to generate parameterized cells using GDSFactory-based layout automation tool GLay…☆13Oct 14, 2024Updated last year
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Projects done for Advanced Digital Design with Verilog. Examples include code for applications like Sobel Edge Detection and DTMF generat…☆12Sep 10, 2018Updated 7 years ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- ☆16May 23, 2024Updated 2 years ago
- ☆16Mar 27, 2024Updated 2 years ago
- ☆14Apr 5, 2023Updated 3 years ago
- A machine learning library focused on deep learning☆11Jun 2, 2015Updated 10 years ago
- Backprop with Low-Precision Activations☆11Oct 28, 2019Updated 6 years ago
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆23Jul 21, 2025Updated 10 months ago
- Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab.☆11Apr 9, 2023Updated 3 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- RTL Synthesis for Fast Arithmetic circuits like Booth encoded Multipliers, Carry Save Adders, Fixed-Point and Floating-Point conversions,…☆21Nov 26, 2018Updated 7 years ago
- A verilog HDL based project to control a servomotor with voice commands from an android phone.☆12Nov 11, 2019Updated 6 years ago
- Project 1.1 Simulate a Skywater 130nm standard cell using ngspice☆14Jul 18, 2025Updated 10 months ago
- Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.☆41Apr 13, 2021Updated 5 years ago
- ☆18Mar 20, 2017Updated 9 years ago
- Verilog design files and Icestudio file for streaming the OV7670 camera using ULX3S FPGA Board☆23Nov 17, 2021Updated 4 years ago
- A classification of battery, bottle, can, and cigarette.☆21Oct 24, 2020Updated 5 years ago