Andrei0105 / MIPS-multi-cycleLinks
MIPS multi cycle Verilog implementation based on Computer Organization and Design by David A. Patterson and John L. Hennessy
☆23Updated 5 years ago
Alternatives and similar repositories for MIPS-multi-cycle
Users that are interested in MIPS-multi-cycle are comparing it to the libraries listed below
Sorting:
- An overview of TL-Verilog resources and projects☆82Updated last month
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆66Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆14Updated 6 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 4 years ago
- This repository contains the results and code for the MLPerf™ Tiny Inference v0.7 benchmark.☆19Updated 2 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Updated 7 years ago
- My implementation of an FPGA Deep Neural Network Hardware Accelerator, moved from my bitbucket☆27Updated 6 years ago
- This repository contains all the information included in the beginner SoC/physical design using open-source EDA tools organized by VLSI S…☆11Updated 4 years ago
- To develop Arm Cortex-M0 based SoCs, from creating high-level functional specifications to design, implementation and testing on FPGA pla…☆38Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- An inhouse RISC-V 32-bits CPU☆18Updated 7 months ago
- North Carolina State University: ECE 745 : Project: LC3 Microcontroller Functional Verification using SystemVerilog☆11Updated 8 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆118Updated 2 years ago
- PQR5ASM is a RISC-V Assembler compliant with RV32I☆19Updated 9 months ago
- FPGA Design of a Neural Network for Color Detection☆82Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆82Updated 2 years ago
- ai_accelerator_basic_for_student (no solve)☆14Updated 5 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆32Updated last year
- FOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already ins…☆107Updated last year
- From Pytorch model to C++ for Vitis HLS☆20Updated this week
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆134Updated 4 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆17Updated 3 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆17Updated 2 years ago
- Basic floating-point components for RISC-V processors☆11Updated 8 years ago
- ☆40Updated 6 years ago
- OpenCL HLS based CNN Accelerator on Intel DE10 Nano FPGA.☆82Updated 2 years ago
- Synthesizable Floating point unit written using Verilog. Supports 32-bit (Single-Precision) Multiplication, Addition and Division and Squ…☆68Updated last year
- Implementation of weight stationary systolic array which has a size of 4x4(scalable) to 256X256☆28Updated last year
- 2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…☆31Updated last year