ConstantPark / Neural-Network-Acceleration-3
☆13Updated 4 years ago
Alternatives and similar repositories for Neural-Network-Acceleration-3
Users that are interested in Neural-Network-Acceleration-3 are comparing it to the libraries listed below
Sorting:
- Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM☆52Updated 5 years ago
- Neural Network Acceleration using CPU/GPU, ASIC, FPGA☆61Updated 4 years ago
- ☆23Updated 3 years ago
- DAC System Design Contest 2020☆29Updated 4 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- This is an implementation of YOLO using LSQ network quantization method.☆23Updated 3 years ago
- ☆70Updated 5 years ago
- Simulator for BitFusion☆99Updated 4 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 4 years ago
- ☆10Updated 5 months ago
- Eyeriss chip simulator☆36Updated 5 years ago
- 2020 xilinx summer school☆17Updated 4 years ago
- ☆14Updated 5 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- Neural Network Quantization With Fractional Bit-widths☆12Updated 4 years ago
- ☆19Updated 4 years ago
- ☆30Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- Approximate layers - TensorFlow extension☆27Updated last month
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- A reference implementation of the Mind Mappings Framework.☆29Updated 3 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆11Updated 3 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- MAERI public release☆31Updated 3 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- MAESTRO binary release☆22Updated 5 years ago
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Updated last year
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆13Updated 5 years ago
- Code for paper "FuSeConv Fully Separable Convolutions for Fast Inference on Systolic Arrays" published at DATE 2021☆14Updated 3 years ago