ConstantPark / Nerual-Network-Acceleration-1Links
Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
☆54Updated 5 years ago
Alternatives and similar repositories for Nerual-Network-Acceleration-1
Users that are interested in Nerual-Network-Acceleration-1 are comparing it to the libraries listed below
Sorting:
- Neural Network Acceleration using CPU/GPU, ASIC, FPGA☆63Updated 5 years ago
- ☆71Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 6 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- ☆19Updated 4 years ago
- ☆31Updated 7 months ago
- ☆23Updated 4 years ago
- ☆16Updated 4 years ago
- HW/SW co-design of sentence-level energy optimizations for latency-aware multi-task NLP inference☆52Updated last year
- ☆35Updated 6 years ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- [TCAD 2021] Block Convolution: Towards Memory-Efficient Inference of Large-Scale CNNs on FPGA☆17Updated 3 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 3 years ago
- ☆62Updated 5 years ago
- [FPGA'21] CoDeNet is an efficient object detection model on PyTorch, with SOTA performance on VOC and COCO based on CenterNet and Co-Desi…☆27Updated 2 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- A DAG processor and compiler for a tree-based spatial datapath.☆14Updated 3 years ago
- ☆35Updated 5 years ago
- An HLS based winograd systolic CNN accelerator☆54Updated 4 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆49Updated 8 months ago
- BISMO: A Scalable Bit-Serial Matrix Multiplication Overlay for Reconfigurable Computing☆146Updated 5 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆59Updated last month
- Digital Design Lab Spring 2019 Final Project☆13Updated 6 years ago
- Eyeriss chip simulator☆38Updated 5 years ago
- ☆72Updated 2 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆59Updated 4 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 3 years ago
- Static Block Floating Point Quantization for CNN☆37Updated 4 years ago
- A Out-of-box PyTorch Scaffold for Neural Network Quantization-Aware-Training (QAT) Research. Website: https://github.com/zhutmost/neuralz…☆25Updated 2 years ago