ConstantPark / Nerual-Network-Acceleration-1Links
Neural Network Acceleration such as ASIC, FPGA, GPU, and PIM
☆52Updated 5 years ago
Alternatives and similar repositories for Nerual-Network-Acceleration-1
Users that are interested in Nerual-Network-Acceleration-1 are comparing it to the libraries listed below
Sorting:
- Neural Network Acceleration using CPU/GPU, ASIC, FPGA☆61Updated 4 years ago
- ☆71Updated 5 years ago
- Provides the code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerators" by Luk…☆19Updated 5 years ago
- ☆19Updated 4 years ago
- [ICML 2021] "Auto-NBA: Efficient and Effective Search Over the Joint Space of Networks, Bitwidths, and Accelerators" by Yonggan Fu, Yonga…☆15Updated 3 years ago
- ☆13Updated 4 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆65Updated 3 years ago
- Approximate layers - TensorFlow extension☆27Updated last month
- This is an implementation of YOLO using LSQ network quantization method.☆23Updated 3 years ago
- Digital Design Lab Spring 2019 Final Project☆11Updated 5 years ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆135Updated 2 years ago
- ☆23Updated 3 years ago
- ☆34Updated 4 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆52Updated last month
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 3 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 3 months ago
- A DAG processor and compiler for a tree-based spatial datapath.☆13Updated 2 years ago
- [ICASSP'20] DNN-Chip Predictor: An Analytical Performance Predictor for DNN Accelerators with Various Dataflows and Hardware Architecture…☆25Updated 2 years ago
- Official implementation of "Searching for Winograd-aware Quantized Networks" (MLSys'20)☆27Updated last year
- Eyeriss chip simulator☆36Updated 5 years ago
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆31Updated 6 years ago
- Lab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017☆29Updated 6 years ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆58Updated 3 years ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆125Updated 3 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 4 years ago
- A FPGA-based neural network inference accelerator, which won the third place in DAC-SDC☆28Updated 3 years ago
- Simulator for BitFusion☆100Updated 4 years ago
- [HPCA 2023] ViTCoD: Vision Transformer Acceleration via Dedicated Algorithm and Accelerator Co-Design☆107Updated last year
- ☆10Updated 6 months ago
- An HLS based winograd systolic CNN accelerator☆52Updated 3 years ago