CMUAbstract / releasesLinks
Meta repository with getting-started info for projects released by Abstract group at CMU
☆17Updated 3 years ago
Alternatives and similar repositories for releases
Users that are interested in releases are comparing it to the libraries listed below
Sorting:
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆97Updated last week
- Memory consistency modelling using Alloy☆31Updated 5 years ago
- PipeProof☆11Updated 6 years ago
- ☆40Updated 4 years ago
- Languages, Tools, and Techniques for Accelerator Design☆33Updated 4 years ago
- The source code to the Voss II Hardware Verification Suite☆56Updated last week
- BTOR2 MLIR project☆26Updated 2 years ago
- CHERI-RISC-V model written in Sail☆66Updated 7 months ago
- A Speculation-Aware Collaborative Dependence Analysis Framework☆28Updated last year
- ☆22Updated this week
- Time-sensitive affine types for predictable hardware generation☆148Updated last month
- FPGA synthesis tool powered by program synthesis☆54Updated last month
- RTLCheck☆25Updated 7 years ago
- Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"☆28Updated 3 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆81Updated last year
- A Language for Closed-form High-level ARchitecture Modeling☆21Updated 6 years ago
- ILA Model Database☆24Updated 5 years ago
- ☆30Updated 3 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆128Updated 3 years ago
- Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python☆13Updated 4 years ago
- Creating beautiful gem5 simulations☆49Updated 4 years ago
- A Hardware Pipeline Description Language☆49Updated 6 months ago
- The MiBench testsuite, extended for use in general embedded environments☆113Updated 13 years ago
- A formalization of the RVWMO (RISC-V) memory model☆36Updated 3 years ago
- ☆104Updated 3 years ago
- Artifact, reproducibility, and testing utilites for gem5☆23Updated 4 years ago
- CoreIR Symbolic Analyzer☆74Updated 5 years ago
- The HW-CBMC and EBMC Model Checkers for Verilog☆101Updated this week
- Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)☆16Updated 2 years ago
- SMTSampler: Efficient Stimulus Generation from Complex SMT Constraints☆31Updated 6 years ago