shuosc / shuorv
SHUOSC RISC-V implementation
☆11Updated 8 months ago
Alternatives and similar repositories for shuorv:
Users that are interested in shuorv are comparing it to the libraries listed below
- A Rust built code judger utils with Web & CLI executables☆18Updated last month
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆109Updated 2 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆46Updated 2 months ago
- 上海大学本科生毕业论文Typst模板☆54Updated last year
- Yet another toy CPU.☆86Updated last year
- Online judge server for Verilog | verilogoj.ustc.edu.cn☆77Updated 6 months ago
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆41Updated 4 years ago
- Source-level operating system debugging tool that supports debugging kernel and multiple user processes synchronously. VSCode integration…☆34Updated last month
- The decoder library for jemu execution and web documentation☆54Updated last year
- CQU Dual Issue Machine☆35Updated 6 months ago
- ☆33Updated 5 years ago
- SHU每日两 报脚本(python实现)☆10Updated 4 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆56Updated 2 years ago
- PLCT实验室实习生社区。☆217Updated last week
- ☆11Updated 6 months ago
- Introduction to Computer Systems (II), Spring 2021☆48Updated 3 years ago
- ☆15Updated last year
- ☆100Updated this week
- RISC-V Development Boards Wandering Project. It is part of the Jiachen Project.☆32Updated this week
- Project magament for porting openEuler to RISC-V☆34Updated last year
- 可移植的 RISC-V 解释执行模拟器。模拟了常见的SoC外设,支持运行主线Linux。A portable RISC-V emulator working in instruction-interpreting way. Common SoC peripherals ar…☆82Updated 3 months ago
- 在自制 RISC-V CPU 和 x86 上运行的现代俄罗斯方块 / Modern tetris that runs on self-made RISC-V CPU and x86 machines.☆18Updated 2 years ago
- HITsz LUG 周报☆20Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆27Updated 9 months ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. (第五届龙芯杯特等奖作…☆34Updated 2 years ago
- rcore-os Developer Blog☆45Updated 3 weeks ago
- ☆14Updated 2 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆71Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated last year