xiesicong / fpga_eth_dual_ov5640Links
fpga读取摄像头数据上传到上位机,720P@60Hz
☆19Updated 4 years ago
Alternatives and similar repositories for fpga_eth_dual_ov5640
Users that are interested in fpga_eth_dual_ov5640 are comparing it to the libraries listed below
Sorting:
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆94Updated 8 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆61Updated last year
- FPGA实现简单的图像处理算法☆62Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆49Updated 5 years ago
- fpga跑sobel识别算法☆43Updated 4 years ago
- 2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件☆39Updated 2 years ago
- 帧差法运动目标检测,基于ZYNQ7020☆78Updated 4 years ago
- This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块:UART接收器、UART发送器、UART转AXI4交互式调…☆268Updated 2 years ago
- 视频旋转(2019FPGA大赛)☆37Updated 5 years ago
- 基于FPGA的三速以太网UDP协议栈设计☆33Updated last year
- Real time face detection based on Arm Cortex-M3 DesignStart and FPGA☆209Updated 2 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆120Updated 2 years ago
- image processing based FPGA☆115Updated 4 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆45Updated last year
- 2023集创赛紫光同创杯一等奖项目☆136Updated last year
- ☆78Updated 2 months ago
- FPGA☆126Updated 5 years ago
- Cortex M0 based SoC☆75Updated 4 years ago
- 2023 集创赛国二。基于脉动阵列写的一个简单的卷积层加速器,支持yolov3-tiny的第一层卷积层计算,可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。☆205Updated last month
- FFT implement by verilog_测试验证已通过☆58Updated 9 years ago
- An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器,为低端FPGA嵌入式系统提供廉价、大容量的存储。☆195Updated 2 years ago
- AXI协议规范中文翻译版☆165Updated 3 years ago
- Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…☆213Updated 2 years ago
- Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.☆162Updated 4 years ago
- Vivado诸多IP,包括图像处理等☆232Updated last year
- 我的数字IC厂库:Verilog HDL; System Vreilog; UVM; ModelSim; Quartus II;☆103Updated 3 years ago
- ARM中通过APB总线连接的UART模块☆69Updated 5 years ago
- FPGA图像处理仿真平台☆27Updated 3 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- ☆66Updated 2 years ago