weirdindiankid / cacheflow
CacheFlow is a Linux kernel module that exposes the contents of the last-level cache on *most* ARM machines.
☆16Updated 7 months ago
Alternatives and similar repositories for cacheflow:
Users that are interested in cacheflow are comparing it to the libraries listed below
- A low-level intermediate representation for hardware description languages☆28Updated 4 years ago
- Embedded Universal DSL: a good DSL for us, by us☆27Updated this week
- Reference Hardware Implementations of Bit Extract/Deposit Instructions☆23Updated 7 years ago
- ☆28Updated 7 months ago
- Sled System Emulator☆28Updated 2 months ago
- A reconfigurable and extensible VLIW processor implemented in VHDL☆31Updated 9 years ago
- code for examining determinism of performance counters☆21Updated 3 years ago
- Microbenchmarks for x86_64 kernel entry methods☆18Updated 2 years ago
- A minimal (really) out-of-tree MLIR example☆36Updated 3 weeks ago
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated last month
- Performance Counter Measurements at the cycle granularity☆18Updated 3 years ago
- Microbenchmarking experiments on Zen 2 machines☆16Updated 2 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- Assemble 128-bit RISC-V☆45Updated last year
- A powerful and modern open-source architecture description language.☆41Updated 7 years ago
- Rag-bag of utilities and scripts that do strange things with ELF files☆17Updated last month
- Port of original MemTest86+ v5.1 to other architectures (RISC-V for now)☆15Updated 4 years ago
- Verilator Porcelain☆42Updated last year
- A C++ Library for Hardware Design and Simulation☆15Updated 4 years ago
- A collection of little open source FPGA hobby projects☆48Updated 4 years ago
- Verilog AST☆21Updated last year
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…☆14Updated 8 months ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆26Updated 3 weeks ago
- A fast RISC-V emulator based on the RISC-V Sail model, and an experimental ARM one☆44Updated this week
- The ISA specification for the ZiCondOps extension.☆19Updated 9 months ago
- The BERI and CHERI processor and hardware platform☆47Updated 7 years ago
- GNU Superoptimizer Version 2☆25Updated 3 years ago
- The website for freeCompilerCamp's classroom tutorials, using Github Pages.☆32Updated 3 years ago
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆25Updated this week