cogbt / COGBTLinks
Compile Optimization Guided Binary Translator (using llvm as infrastructure)
☆52Updated last year
Alternatives and similar repositories for COGBT
Users that are interested in COGBT are comparing it to the libraries listed below
Sorting:
- My knowledge base☆78Updated last week
- Unofficial LoongArch Intrinsics Guide☆68Updated last month
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Updated last year
- CPU micro benchmarks☆76Updated 3 weeks ago
- ☆23Updated 2 years ago
- hypocaust-2, a type-1 hypervisor with H extension run on RISC-V machine☆59Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- Examine and discover LoongArch instructions☆22Updated 7 months ago
- A Symmetric Multiprocessing OS Kernel over RISC-V☆32Updated 3 years ago
- Yet another toy CPU.☆92Updated 2 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Updated 4 years ago
- 龙芯产品公开文档存档 / Archive of Loongson products' public documentation☆92Updated last week
- Implements kernels with RISC-V Vector☆22Updated 2 years ago
- 项目的主仓库☆26Updated 3 years ago
- ☆42Updated 2 years ago
- [No longer active] A fork of OpenSBI, with software-emulated hypervisor extension support☆42Updated 5 months ago
- PoC LoongArch - RISC-V emulator☆33Updated 2 years ago
- Paging Debug tool for GDB using python☆13Updated 3 years ago
- 裸金属二进制翻译器的设计和实现☆47Updated 10 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- Loongarch Emulator☆19Updated 10 months ago
- Microarchitecture diagrams of several CPUs☆46Updated last week
- Backend & Frontend for JieLabs☆22Updated 2 years ago
- HyperBench: A Benchmark Suite for Virtualization Capabilities☆32Updated 6 years ago
- safe type-1 Rust Hypervisor for edge devices☆165Updated last week
- My RV64 CPU (Work in progress)☆19Updated 3 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆309Updated last week
- uCore MIPS32 porting☆18Updated 6 years ago
- Recommended coding standard of Verilog and SystemVerilog.☆36Updated 4 years ago
- Project magament for porting openEuler to RISC-V☆34Updated 2 years ago