Alternatives and similar repositories for context-dependent-environments:

Users that are interested in context-dependent-environments are comparing it to the libraries listed below

• ucb-art / fft
  ☆21Updated 4 years ago
• j-marjanovic / chisel-bfm-tester
  BFM Tester for Chisel HDL
  ☆14Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 8 months ago
• TsaiAnson / verif
  ☆11Updated 3 years ago
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆65Updated 5 years ago
• ucb-ucie / uciedigital
  Pure digital components of a UCIe controller
  ☆50Updated this week
• easysoc / layered-firrtl
  This repository is outdated and the related functionality has been migrated to https://github.com/easysoc/easysoc-firrtl
  ☆11Updated 3 years ago
• maltanar / axi-in-chisel
  Examples for creating AXI-interfaced peripherals in Chisel
  ☆73Updated 9 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆57Updated last year
• chick / visualizer
  Provides dot visualizations of chisel/firrtl circuites
  ☆12Updated 5 years ago
• maltanar / fpga-tidbits
  Chisel components for FPGA projects
  ☆119Updated last year
• yaozhaosh / chisel-aes
  Chisel implementation of AES
  ☆23Updated 4 years ago
• freechipsproject / diagrammer
  Provides dot visualizations of chisel/firrtl circuits
  ☆119Updated last year
• RIOSLaboratory / OpenXRAM
  sram/rram/mram.. compiler
  ☆30Updated last year
• rameloni / tywaves-chisel
  A repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code…
  ☆30Updated 2 months ago
• bespoke-silicon-group / bsg_fakeram
  fakeram generator for use by researchers who do not have access to commercial ram generators
  ☆34Updated 2 years ago
• RoaLogic / ahb3lite_pkg
  Common SystemVerilog package used by all RoaLogic IP with AMBA AHB3-Lite interfaces
  ☆16Updated 8 months ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆41Updated 4 years ago
• verilator / uvm
  Universal Verification Methodology (UVM) base libraries, with edits for Verilator
  ☆25Updated 4 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• csail-csg / pyverilator
  Python wrapper for verilator model
  ☆79Updated 11 months ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 8 months ago
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• amiq-consulting / amiq_eth
  Library defining all Ethernet packets in SystemVerilog and in SystemC
  ☆36Updated 8 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 9 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• chipsalliance / diplomacy
  ☆18Updated 6 months ago
• rhit-neuro / deca
  ☆21Updated 4 years ago
• freechipsproject / chisel-testers
  Provides various testers for chisel users
  ☆101Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆63Updated 5 years ago