Asynchronous OS kernel written in Rust.
☆32Nov 27, 2020Updated 5 years ago
Alternatives and similar repositories for aCore
Users that are interested in aCore are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 实现和扩展RISC-V SBI运行时,使之能够支持并运行操作系统☆14Apr 1, 2025Updated last year
- [AFK] Hardware router in Chisel (THU Network Joint Lab 2020)☆14Oct 8, 2020Updated 5 years ago
- Booting multi-processors on x86 bare-metal.☆12Feb 25, 2022Updated 4 years ago
- 各类内核的设计思路☆19May 19, 2021Updated 5 years ago
- ☆13Jul 26, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Rust support for RISC-V Platform-Level Interrupt Controller☆10Oct 13, 2022Updated 3 years ago
- ☆22May 30, 2025Updated last year
- rCore_tutorial_tests☆11Aug 8, 2021Updated 4 years ago
- Tomasulo Simulator written in React as the project for Computer Architecture course, Spring 2019, Tsinghua University☆12Jun 9, 2019Updated 7 years ago
- ☆31Jun 1, 2023Updated 3 years ago
- A simple USB to UART board designed with KiCad.☆14May 4, 2023Updated 3 years ago
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- Decaf 实验综述☆12Jan 7, 2020Updated 6 years ago
- Bare-metal multithreading on multi-core processor.☆18Sep 16, 2022Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- [WIP] Tutorial for zCore kernel.☆59Aug 28, 2021Updated 4 years ago
- Game Engine From Scratch -- Rust China Conference 2020 topic by LemonHX and his team.☆14Dec 16, 2020Updated 5 years ago
- Backend & Frontend for JieLabs☆22Mar 3, 2023Updated 3 years ago
- Relaxed Rust (for cats)☆14Nov 20, 2019Updated 6 years ago
- RISC-V Proxy Kernel for Education☆29Dec 5, 2023Updated 2 years ago
- Handle TrapFrame across kernel and user space on multiple ISAs.☆35Jan 13, 2026Updated 4 months ago
- Low level access to RISCV processors☆22Oct 3, 2022Updated 3 years ago
- A summary of my projects☆49Dec 29, 2025Updated 5 months ago
- 网络学堂 PC 端 App☆21May 28, 2026Updated last week
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- The virtual console embedded in rCore kernel.☆11May 6, 2025Updated last year
- 在RISC-V处理器上实现一个轻量级的Hypervisor。☆12Dec 25, 2020Updated 5 years ago
- Framework of pa code for THU compiler principle course.☆13Dec 18, 2019Updated 6 years ago
- ☆82Mar 5, 2021Updated 5 years ago
- Some notes or translations about operating system or programming language.☆99Nov 10, 2024Updated last year
- Superscalar RISC-V processor written in Clash.☆35Aug 23, 2022Updated 3 years ago
- OS教学实验:用Rust&C实现各种历史上的经典OS Kernels的实例☆45Apr 17, 2022Updated 4 years ago
- 洛佳的异步内核实验室☆25May 22, 2021Updated 5 years ago
- Tutorial doc for rCore OS step by step (2nd edition)☆65Nov 19, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- [Experiment] JNeT: japaric's network thingies☆28Nov 17, 2019Updated 6 years ago
- Multi-arch instruction set simulator that is 6666. Contributions welcomed!☆16Jun 8, 2020Updated 6 years ago
- The x86_64 UEFI bootloader for rCore☆43Mar 1, 2026Updated 3 months ago
- 可运行OS的RISCV-64的硬件模拟器设计与实现☆22Mar 26, 2021Updated 5 years ago
- User-mode trap-and-emulate hypervisor for RISC-V☆14Feb 11, 2022Updated 4 years ago
- The new Decaf compiler, rewritten in "modern" Java☆67Jul 21, 2020Updated 5 years ago
- 快速陷入处理☆40Jan 22, 2026Updated 4 months ago