Alternatives and similar repositories for open_sld

Users that are interested in open_sld are comparing it to the libraries listed below

• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆57Updated last year
• hdl-util / sdram-controller
  Generic FPGA SDRAM controller, originally made for AS4C4M16SA
  ☆83Updated 5 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 4 years ago
• ZipCPU / wbscope
  A wishbone controlled scope for FPGA's
  ☆87Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆124Updated 2 years ago
• hdl4fpga / hdl4fpga
  VHDL library 4 FPGAs
  ☆185Updated this week
• amaranth-farm / amlib
  assorted library of utility cores for amaranth HDL
  ☆102Updated last year
• ldoolitt / vhd2vl
  ☆139Updated 3 weeks ago
• f4pga / prjxray-db
  Project X-Ray Database: XC7 Series
  ☆74Updated 4 years ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆141Updated 4 years ago
• cliffordwolf / PonyLink
  A single-wire bi-directional chip-to-chip interface for FPGAs
  ☆125Updated 9 years ago
• stnolting / fpga_torture
  🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.
  ☆32Updated 3 years ago
• wavedrom / vcd-samples
  sample VCD files
  ☆41Updated last month
• yrrapt / amsat_txrx_ic
  An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)
  ☆73Updated 4 years ago
• blackmesalabs / hyperram
  Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC
  ☆93Updated 7 years ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆187Updated last year
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆119Updated 4 years ago
• VLSI-EDA / PoC-Examples
  This repository contains synthesizable examples which use the PoC-Library.
  ☆39Updated 5 years ago
• apertus-open-source-cinema / naps
  An experiment for building gateware for the axiom micro / beta using amaranth-hdl
  ☆45Updated 8 months ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆86Updated last year
• duskwuff / Xilinx-ISE-Makefile
  An example of how to use the Xilinx ISE toolchain from the command line
  ☆62Updated 6 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆97Updated 5 years ago
• enjoy-digital / litesata
  Small footprint and configurable SATA core
  ☆161Updated 3 weeks ago
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆53Updated 2 years ago
• qermit / WishboneAXI
  Wishbone to AXI bridge (VHDL)
  ☆44Updated 6 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆84Updated 5 years ago
• f4pga / prjuray
  Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
  ☆82Updated 3 years ago
• quartiq / bscan_spi_bitstreams
  FPGA gateware and pre-build bitstreams that expose SPI over JTAG. The protocol is implemented (among others) by openocd.
  ☆58Updated 2 years ago
• Ravenslofty / 74xx-liberty
  ☆70Updated 2 years ago
• SpinalHDL / openocd_riscv
  Spen's Official OpenOCD Mirror
  ☆51Updated 10 months ago