Read chapters directly from this repo - do not use GitHub Pages link.
☆119Jul 25, 2026Updated 3 weeks ago
Alternatives and similar repositories for riscv-vector-primer
Users that are interested in riscv-vector-primer are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆14Apr 28, 2026Updated 3 months ago
- Telegram Bot for YTU Dining Hall Menu☆15May 9, 2022Updated 4 years ago
- ☆26Updated this week
- Modular RISC-V implementation & SoC☆17Aug 3, 2026Updated 2 weeks ago
- RISC-V Core Local Interrupt Controller (CLINT)☆33Aug 7, 2026Updated last week
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- This repository contains a RISC-V System-on-Chip (SoC) design files implemented in SystemVerilog☆18Feb 9, 2025Updated last year
- Links to the RVfpga materials developed by Imagination Technologies, and recent additions on teaching materials and experiences, papers, …☆38Aug 7, 2026Updated last week
- Python client SDK for the Qumulator quantum computing API☆20Jul 26, 2026Updated 3 weeks ago
- Unit tests generator for RVV 1.0☆115May 25, 2026Updated 2 months ago
- 3.3V SRAM macros for GF180MCU, based on the original 5V SRAM macros.☆23Jun 19, 2026Updated last month
- CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontroller…☆11Jul 21, 2020Updated 6 years ago
- A sample of using VGA mode 13h on a QEMU RISC-V virt machine.☆16Jun 24, 2025Updated last year
- ☆22Aug 8, 2023Updated 3 years ago
- fbDOOM with RISC-V Vector optimizations☆17Aug 30, 2023Updated 2 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Handle Fast Signal Traces (fst) in Python☆16Jun 11, 2025Updated last year
- Daisytuner Optimizing Compiler Collection (docc)☆22Updated this week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…☆181Feb 2, 2026Updated 6 months ago
- High quality and composable RTL libraries in SystemVerilog☆47Updated this week
- Intel Management Engine JTAG Proof of Concept☆21Nov 14, 2019Updated 6 years ago
- ☆19Feb 24, 2026Updated 5 months ago
- spike-vp☆13Feb 5, 2024Updated 2 years ago
- Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools☆210Updated this week
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- RISC-V port of GDB☆16Mar 9, 2026Updated 5 months ago
- A double JIT VM☆23Jul 9, 2026Updated last month
- A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.☆21Updated this week
- List of several designs I have been working through the years to avoid re-designing it again☆16Jun 17, 2024Updated 2 years ago
- Original RISC-V 1.0 implementation. Not supported.☆44Oct 4, 2018Updated 7 years ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,735Updated this week
- Translate RISC-V Vector Assembly from v1.0 to v0.7☆37Aug 21, 2024Updated last year
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆166Updated this week
- 42 school project, Path Tracing, OpenCL, Multicluster☆11Mar 14, 2019Updated 7 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- A 4x4 Weight Stationary Systolic Array Implementation☆15Oct 16, 2023Updated 2 years ago
- Creat your .gitignore files with CLI☆14Jan 17, 2022Updated 4 years ago
- Fuzzing for SpinalHDL☆17Oct 10, 2022Updated 3 years ago
- Digital Design Equivalence Checking☆99Updated this week
- ☆23Apr 24, 2026Updated 3 months ago
- ☆10Jan 26, 2023Updated 3 years ago
- Subroutines which implement RISC-V multiplication, division, base conversion, square root, and other integer algorithms☆22Jul 7, 2026Updated last month