The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
☆79Apr 24, 2020Updated 6 years ago
Alternatives and similar repositories for RiscvSpecFormal
Users that are interested in RiscvSpecFormal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bl…☆233Aug 31, 2020Updated 6 years ago
- RISC-V Specification in Coq☆123Updated this week
- Kami based processor implementations and specifications☆23Jun 8, 2020Updated 6 years ago
- A formal semantics of the RISC-V ISA in Haskell☆181Aug 13, 2023Updated 3 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆77Jun 18, 2020Updated 6 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- A formalization of bitset operations in Coq and the corresponding axiomatization and extraction to OCaml native integers [maintainer=@ant…☆25Mar 3, 2026Updated 8 months ago
- Formal specification of RISC-V Instruction Set☆103Jun 29, 2020Updated 6 years ago
- ☆11Nov 19, 2015Updated 10 years ago
- Formalization in Coq of algorithms used in compilers for the Compiler.org project☆15Dec 22, 2018Updated 7 years ago
- ☆15Oct 24, 2017Updated 9 years ago
- COATCheck☆14Nov 4, 2018Updated 8 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆175Sep 17, 2026Updated last month
- Formal specification and verification of hardware, especially for security and privacy.☆133May 19, 2022Updated 4 years ago
- ☆21Aug 1, 2015Updated 11 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Verified Software Toolchain☆518Updated this week
- ☆20Mar 15, 2016Updated 10 years ago
- RTLCheck☆26Oct 9, 2018Updated 8 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆101Jan 29, 2026Updated 9 months ago
- CoreIR Symbolic Analyzer☆75Oct 27, 2020Updated 6 years ago
- A Formal Library about Elliptic Curves for the Mathematical Components Library.☆15Nov 10, 2021Updated 5 years ago
- A Probability Theory Library for the Coq Theorem Prover☆56Oct 6, 2023Updated 3 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- PipeProof☆11Dec 18, 2019Updated 6 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆106Jun 27, 2022Updated 4 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆205Dec 3, 2020Updated 5 years ago
- Experiments in Synthetic Differential Geometry☆16Jul 1, 2021Updated 5 years ago
- Build an educational formally verified version of the Nand 2 Tetris course using Coq (and other formal tools).☆60Dec 24, 2021Updated 4 years ago
- Coq formalizations of functional languages.☆147Jul 2, 2020Updated 6 years ago
- VERified asSembler for cryptographic primitives☆12Jul 15, 2023Updated 3 years ago
- A core language for rule-based hardware design 🦑☆191Dec 10, 2025Updated 11 months ago
- "An Altruistic Processor", implemented in CLaSH (WARNING: incomplete code)☆13Mar 31, 2017Updated 9 years ago
- A function definition package for Rocq☆239Updated this week
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A well typed interpreter for the simply-typed lambda calculus written in Agda☆11Aug 22, 2016Updated 10 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- RISC-V Formal Verification Framework☆635Apr 6, 2022Updated 4 years ago
- Sail architecture definition language☆972Updated this week
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆192Apr 4, 2026Updated 7 months ago
- ☆22Dec 29, 2014Updated 11 years ago
- RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)☆344Jan 23, 2022Updated 4 years ago
Are these results useful?