The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
☆79Apr 24, 2020Updated 6 years ago
Alternatives and similar repositories for RiscvSpecFormal
Users that are interested in RiscvSpecFormal are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Kami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bl…☆232Aug 31, 2020Updated 6 years ago
- Kami based processor implementations and specifications☆23Jun 8, 2020Updated 6 years ago
- RISC-V Specification in Coq☆119Sep 18, 2026Updated 2 weeks ago
- A formal semantics of the RISC-V ISA in Haskell☆177Aug 13, 2023Updated 3 years ago
- Locus site for Public Review of Several RISC-V ISA Formal Specs☆76Jun 18, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Formal specification of RISC-V Instruction Set☆102Jun 29, 2020Updated 6 years ago
- ☆12Feb 11, 2019Updated 7 years ago
- ☆20Mar 15, 2016Updated 10 years ago
- A work-in-progress language and compiler for verified low-level programming☆336Sep 22, 2026Updated last week
- Verified Software Toolchain☆508Updated this week
- Proofs of the number of inhabitants of polymorphic functions☆23Jul 19, 2018Updated 8 years ago
- A Platform for High-Level Parametric Hardware Specification and its Modular Verification☆170Sep 17, 2026Updated 2 weeks ago
- ☆15Oct 24, 2017Updated 8 years ago
- Coq formalizations of functional languages.☆144Jul 2, 2020Updated 6 years ago
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Compiler for type theoretic lambda calculi equipped with system primtives which compiles side-effecting, strict expressions into efficien…☆43Jul 27, 2019Updated 7 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆205Dec 3, 2020Updated 5 years ago
- A formalization of bitset operations in Coq and the corresponding axiomatization and extraction to OCaml native integers [maintainer=@ant…☆25Mar 3, 2026Updated 7 months ago
- PipeProof☆11Dec 18, 2019Updated 6 years ago
- Sail architecture definition language☆948Updated this week
- Formalisation of the linear lambda calculus in Coq☆10Dec 2, 2018Updated 7 years ago
- Galois RISC-V ISA Formal Tools☆61May 6, 2026Updated 4 months ago
- Experiments in Synthetic Differential Geometry☆16Jul 1, 2021Updated 5 years ago
- "An Altruistic Processor", implemented in CLaSH (WARNING: incomplete code)☆13Mar 31, 2017Updated 9 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- ☆21Aug 1, 2015Updated 11 years ago
- Provides a packaged collection of open source EDA tools☆12Apr 14, 2019Updated 7 years ago
- A core language for rule-based hardware design 🦑☆187Dec 10, 2025Updated 9 months ago
- Sail RISC-V model☆778Updated this week
- A Library for Representing Recursive and Impure Programs in Coq☆259Jun 12, 2026Updated 3 months ago
- firrtlator is a FIRRTL C++ library☆23Dec 15, 2016Updated 9 years ago
- ☆10Nov 19, 2015Updated 10 years ago
- ☆16Dec 28, 2021Updated 4 years ago
- Formal specification and verification of hardware, especially for security and privacy.☆133May 19, 2022Updated 4 years ago
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- A Formal Library about Elliptic Curves for the Mathematical Components Library.☆15Nov 10, 2021Updated 4 years ago
- FPGA-Accelerated Simulation Framework Automatically Transforming Arbitrary RTL☆103Nov 22, 2019Updated 6 years ago
- Type-level assertion operators☆16Mar 20, 2018Updated 8 years ago
- The ANUBIS benchmark suite for Incremental Synthesis☆12Dec 15, 2020Updated 5 years ago
- RISC-V Formal Verification Framework☆634Apr 6, 2022Updated 4 years ago
- A formally verified high-level synthesis tool based on CompCert and written in Coq.☆100Jan 29, 2026Updated 8 months ago
- Iodine: Verifying Constant-Time Execution of Hardware☆18Mar 29, 2021Updated 5 years ago