☆28Mar 30, 2022Updated 3 years ago
Alternatives and similar repositories for gurulang
Users that are interested in gurulang are comparing it to the libraries listed below
Sorting:
- A Simple XML Document Database (University Project)☆10May 30, 2022Updated 3 years ago
- A linux PCIe driver for Altera☆11Oct 9, 2018Updated 7 years ago
- Framework for writing tests for RISC-V CPU/SOC validation.☆11Jan 19, 2026Updated last month
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- SDN Laboratory☆11May 6, 2021Updated 4 years ago
- this folder contains different algorithms implemented on FPGA☆10Dec 30, 2023Updated 2 years ago
- SoC for muntjac☆13Jun 18, 2025Updated 8 months ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆17Nov 15, 2022Updated 3 years ago
- SHA3-256 MINER CORE☆14Aug 30, 2020Updated 5 years ago
- MESMERIC: A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies☆10Oct 1, 2020Updated 5 years ago
- The systems bred pastebin | Easiest pastebin of the west!☆12Jul 8, 2023Updated 2 years ago
- a small simple slow serial FPGA core☆16Mar 11, 2021Updated 4 years ago
- SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.☆12Jun 28, 2020Updated 5 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆13Sep 8, 2020Updated 5 years ago
- ☆16Jul 10, 2025Updated 8 months ago
- Playground for implementing LDPC codes on FPGA☆17Jan 1, 2023Updated 3 years ago
- Running Rust on the (Linux) Litex VexRiscv FPGA SOC☆15Jun 3, 2025Updated 9 months ago
- Baremetal Backtracing on RISC-V☆16Jun 22, 2021Updated 4 years ago
- TinyQV - Crowdsourced Risc-V SoC☆35Oct 20, 2025Updated 4 months ago
- Public Release Repo for PhIDO, currently maintained.☆30Feb 24, 2026Updated 2 weeks ago
- Parasitic capacitance analysis of foundry metal stackups☆17Jan 12, 2026Updated last month
- Presentation for pt-three-ways - a CppCon 2019 presentation☆14Jan 23, 2025Updated last year
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 5 months ago
- FPGA referrence implementation for aion equihash 2109☆16Aug 1, 2018Updated 7 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Repository for Hornet RISC-V Core☆19Sep 15, 2022Updated 3 years ago
- Algebraic methods for construction QC-LDPC and cyclic LDPC LDGM EG-LDPC source codes☆19Dec 1, 2024Updated last year
- ☆17Oct 9, 2023Updated 2 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 21, 2024Updated last year
- ☆16Aug 20, 2024Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆83Feb 5, 2026Updated last month
- ☆16Mar 14, 2023Updated 2 years ago
- A utility for testing and building software modules☆14May 29, 2024Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- pLUTo is a DRAM-based Processing-using-Memory architecture that leverages the high density of DRAM to enable the massively parallel stori…☆18Jan 12, 2023Updated 3 years ago
- CXL Memory Resource Kit top-level repository☆20Dec 13, 2023Updated 2 years ago
- RISC-V Superscalar Educational Simulator based on Tomasulo's Algorithm☆27Nov 1, 2025Updated 4 months ago
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆26Aug 16, 2023Updated 2 years ago
- Polybar plugin for Spotify☆15Nov 10, 2024Updated last year