☆28Mar 30, 2022Updated 4 years ago
Alternatives and similar repositories for gurulang
Users that are interested in gurulang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Baremetal Backtracing on RISC-V☆16Jun 22, 2021Updated 5 years ago
- A linux PCIe driver for Altera☆11Oct 9, 2018Updated 7 years ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- Framework for writing tests for RISC-V CPU/SOC validation.☆11Jan 19, 2026Updated 6 months ago
- MESMERIC: A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies☆10Oct 1, 2020Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- SoC for muntjac☆14Jun 18, 2025Updated last year
- Docker image for NS-3 Network Simulator v.3.30☆13Apr 11, 2021Updated 5 years ago
- a small simple slow serial FPGA core☆16Mar 11, 2021Updated 5 years ago
- Running Rust on the (Linux) Litex VexRiscv FPGA SOC☆16Jun 3, 2025Updated last year
- DE10 NANO SHA3-256 Proof of Work Miner☆14Sep 8, 2020Updated 5 years ago
- Direct Access Memory for MPSoC☆13Jun 16, 2026Updated last month
- SDN Laboratory☆10May 6, 2021Updated 5 years ago
- this folder contains different algorithms implemented on FPGA☆13Dec 30, 2023Updated 2 years ago
- SHA3-256 MINER CORE☆14Aug 30, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Simple XML Document Database (University Project)☆10May 30, 2022Updated 4 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆18Nov 15, 2022Updated 3 years ago
- The systems bred pastebin | Easiest pastebin of the west!☆12Jul 8, 2023Updated 3 years ago
- ⭕ Tricky, super fast and dumb JSON library for C/C++☆20Dec 12, 2023Updated 2 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated 2 months ago
- ☆17Jul 10, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.☆13Jun 28, 2020Updated 6 years ago
- A dead simple template manager for neovim written in lua☆23Aug 21, 2021Updated 4 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Repository for compilation and cycle-accurate simulator for scale-out systolic arrays☆16Jan 4, 2023Updated 3 years ago
- FPGA referrence implementation for aion equihash 2109☆16Aug 1, 2018Updated 7 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 19, 2026Updated 4 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆17Jun 30, 2026Updated 3 weeks ago
- A utility for testing and building software modules☆14May 29, 2024Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆93Updated this week
- A simple CPU ray tracer written in Rust☆22Mar 10, 2023Updated 3 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 9 months ago
- ☆17Oct 9, 2023Updated 2 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Playground for implementing LDPC codes on FPGA☆17Jan 1, 2023Updated 3 years ago
- Quick'n'dirty FuseSoC+cocotb example☆20Nov 26, 2024Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P with Zfinx and Zce ISA extentions☆27Aug 16, 2023Updated 2 years ago
- Viam Server for Microcontrollers☆20Jun 22, 2026Updated last month
- Repository for Hornet RISC-V Core☆21Sep 15, 2022Updated 3 years ago
- Command line interface for cricket enthusiasts☆19Feb 25, 2021Updated 5 years ago
- ☆16Aug 20, 2024Updated last year