☆28Mar 30, 2022Updated 4 years ago
Alternatives and similar repositories for gurulang
Users that are interested in gurulang are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A pure implementation of the decorator pattern☆11Apr 20, 2019Updated 7 years ago
- Mark an endpoint as deprecated so everyone knows its going away!☆27Jun 14, 2019Updated 7 years ago
- Baremetal Backtracing on RISC-V☆16Jun 22, 2021Updated 5 years ago
- A linux PCIe driver for Altera☆11Oct 9, 2018Updated 7 years ago
- Source code for the "YouTube on Rails" article on SitePoint.☆18Feb 2, 2015Updated 11 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- Framework for writing tests for RISC-V CPU/SOC validation.☆11Jan 19, 2026Updated 5 months ago
- RISCulator is a RISC-V emulator.☆12Aug 18, 2023Updated 2 years ago
- MESMERIC: A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies☆10Oct 1, 2020Updated 5 years ago
- SoC for muntjac☆13Jun 18, 2025Updated last year
- Docker image for NS-3 Network Simulator v.3.30☆13Apr 11, 2021Updated 5 years ago
- Running Rust on the (Linux) Litex VexRiscv FPGA SOC☆16Jun 3, 2025Updated last year
- a small simple slow serial FPGA core☆16Mar 11, 2021Updated 5 years ago
- ☆17Jul 10, 2025Updated 11 months ago
- cross platform clipboard library☆18Oct 16, 2023Updated 2 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- database storage for paperclip☆20Oct 4, 2019Updated 6 years ago
- Direct Access Memory for MPSoC☆13Jun 16, 2026Updated 2 weeks ago
- SDN Laboratory☆10May 6, 2021Updated 5 years ago
- this folder contains different algorithms implemented on FPGA☆13Dec 30, 2023Updated 2 years ago
- ITS ALIVE!!!!!!! (or is it?)☆15Sep 18, 2020Updated 5 years ago
- A Simple XML Document Database (University Project)☆10May 30, 2022Updated 4 years ago
- The systems bred pastebin | Easiest pastebin of the west!☆12Jul 8, 2023Updated 2 years ago
- Source code of the U-TRR methodology presented in "Uncovering In-DRAM RowHammer Protection Mechanisms: A New Methodology, Custom RowHamme…☆18Nov 15, 2022Updated 3 years ago
- DE10 NANO SHA3-256 Proof of Work Miner☆14Sep 8, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ⭕ Tricky, super fast and dumb JSON library for C/C++☆20Dec 12, 2023Updated 2 years ago
- Our contribution to the AMD Open Hardware Contest: A ML-based Deep Packet Inspection for RDMA-networking on FPGAs☆13May 6, 2026Updated last month
- Presentation for pt-three-ways - a CppCon 2019 presentation☆14Jan 23, 2025Updated last year
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- A dead simple template manager for neovim written in lua☆23Aug 21, 2021Updated 4 years ago
- SAP-1 CPU in Verilog for the Mojo FPGA board - has seperate address bus.☆13Jun 28, 2020Updated 6 years ago
- FPGA referrence implementation for aion equihash 2109☆16Aug 1, 2018Updated 7 years ago
- Open-source thin-and-light 13" laptop☆68Jun 2, 2026Updated last month
- Public Release Repo for PhIDO, currently maintained.☆41Jun 17, 2026Updated 2 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Code example for http://blog.littleblimp.com/post/53942611764/direct-uploads-to-s3-with-rails-paperclip-and☆30May 11, 2014Updated 12 years ago
- Set up your GitHub Actions workflow with a OSS CAD Suite☆16Mar 19, 2026Updated 3 months ago
- diablo is an Out-Of-Order 64-bit RISC-V processor.☆17Jun 23, 2026Updated last week
- A utility for testing and building software modules☆14May 29, 2024Updated 2 years ago
- Some neorv32 examples for Intel FPGA boards using Quartus II and SEGGER Embedded Studio for RISC-V.☆15Oct 5, 2025Updated 8 months ago
- ☆17Oct 9, 2023Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆92Jun 25, 2026Updated last week